STMicroelectronics SPC572L series Reference Manual page 1229

RM0400 LVDS Fast Asynchronous Serial Transmission (LFAST) – Interprocessor Communica-
Field
LFAST Receiver Enable. This bit controls the reception of the frames and decoding on the LFAST
device. This bit also disables the Rx LVDS LR.
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0 Receiver Interface is disabled. If this bit is cleared during a data transfer, the current frame is
RXEN
received and then the Rx block is disabled. After the Rx block is disabled, all new frames from
LFAST peer device are ignored. System Side Module Rx interface is not disabled by this bit.
1 Receiver Interface is Enabled.
LFAST Transmitter Enable. This bit controls the transmission of frames from the LFAST device and
disables the Tx LVDS LD. This bit can also be set and cleared by LFAST slave H/W on reception of
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an ICLC command frame.
TXEN
0 LFAST transmitter Interface is disabled. No new request is accepted but ongoing request is served.
1 Transmitter is Enabled.
19-26 Reserved
Tx Arbiter Disable. This bit enables/disables the Tx block arbiter. Current frame transfer is
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completed, but new frame requests are ignored.
TXARBD
0 Enable Tx arbiter and framer. When enabled it takes all the frame request and services based on
priority.
1 Disable Tx arbiter and framer. All frame requests are ignored.
CTS Enable. This bit defines the Push-Pull mode of the LFAST devices receiver. This bit is used to
enable/disable CTS mode of the Tx block.
0 CTS mode is disabled. Indicates that the device is in Push mode. The CTS bit of frames transmitted
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is 1. The CTS bit does not represent the status of Rx FIFO.
CTSEN
1 CTS mode is enabled. The CTS bit of all transmit frames is set when the Rx FIFO empty space is
on or above higher threshold, and cleared when the Rx FIFO empty space is on or below lower
threshold.
29 Reserved
LFAST Soft Reset. This bit is automatically cleared after reset.
30
0 No soft reset.
DRFRST 1 Soft reset to LFAST is asserted. When set it causes a reset of the LFAST module; all the registers
will be reset to their default values and all the FIFOs will be flushed.
DATA Frame Enable. This bit enables/disables the transmission and reception of data frames
between the LFAST master and slave devices.
31
0 Data frame transmission and reception is disabled. Tx data frame requests are ignored by the
DATAEN transmitter. Frame with LCT of data frame is ignored by the receiver.
1 Data frame transmission and reception is enabled. Tx data frame requests are serviced by the
transmitter. Frame with LCT of data frame is received and placed into the Rx data FIFO.
47.6.2.2 Speed Control Register (SCR)
The SCR is used to configure the Rx and Tx data rate of the LFAST.
Table 656. MCR field descriptions(Continued)
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Description
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