STMicroelectronics SPC572L series Reference Manual page 1395

RM0400
Field
Pause Pulse Diagnostic Check Selection: This bit controls which diagnostic checks to run when
messages are enabled to be received with pause pulses.
18
PP_CHKSEL
0 – Both Successive Calibration Pulse Check and Pause Pulse Diagnostic are run
1 – Only Pause Pulse Diagnostic is run. Successive Calibration Pulse Check is disabled.
Fast Message CRC Type. This indicates the type of CRC method to be used for CRC Diagnostic
Check on the received fast messages
19
FCRC_TYPE
0 – XOR based implementation (Recommended by SAE Specification)
1 – Legacy LUT based implementation
Fast Message CRC Status and Communication Nibble Enable. This bit enables the inclusion of
Status and Communication Nibble when CRC is calculated for Fast Messages.
20
FCRC_SC_E
N 0 – Status and Communication Nibble not included in CRC calculation
1 – Status and Communication Nibble is included in CRC calculation
Slow Serial Message CRC Type. This indicates the type of CRC method to be used for CRC
Diagnostic Check on the received slow serial messages.
21
SCRC_TYP
E 0 – XOR based implementation (Recommended by SAE Specification)
1 – Legacy LUT based implementation
Pause Pulse Enable. Enables the channel receiver to detect a pause pulse.
22
PAUSE_EN 0 – Detection of Pause Pulse is disabled
1 – Detection of Pause Pulse enabled
Successive Calibration Pulse Check Method. This bit indicates the method to be used for performing
the successive calibration pulse check. Default value is 1.
23
SUCC_CAL_
CHK 0 – Option 2 i.e. Low Latency Option as per SAE Specification
1 – Option 1 i.e. Preferred but High Latency Option as per SAE Specification
Input Filter Sample Count. This indicates the number of Protocol Clock (of High Frequency Receiver
Clock) cycles required for channel input from device's pad to remain stable before it is sampled as 0
or 1. This field defines the width of glitches to be filtered out by the input programmable filter on that
channel. Only one bit should be set in this field and the output of filter will be offset by twice the
24:31
same number of clocks plus additional 3 clocks due to synchronization. Default value is '4'.
FIL_CNT
0 – No filtering. Input from device's pad is only synchronized
Non-Zero – Filtering is enabled
49.3.2.21 Channel 'n' Fast Message Data Read Register (n = 0 to (CH-1))
(CHn_FMSG_DATA)
Address offset: 0x0160 + 0x18 × n
This is register CHn_FMSG_DATA. The contents of this register are same as
Section 49.3.2.12: DMA Fast Message Data Read Register
Table 809. CHn_CONFIG field descriptions(Continued)
DocID027809 Rev 4
Description
(DMA_FMSG_DATA).
SENT Receiver (SRX)
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