Memory Organization; Introduction; Memory Map And Register Boundary Addresses; Table 2. Stm32F05Xxx Memory Map And Peripheral Register Boundary Addresses - STMicroelectronics STM32F05 series Reference Manual

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2.2

Memory organization

2.2.1

Introduction

Program memory, data memory, registers and I/O ports are organized within the same linear
4-Gbyte address space.
The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word
is considered the word's least significant byte and the highest numbered byte the most
significant.
The addressable memory space is divided into 8 main blocks, each of 512 MB.
All the memory areas that are not allocated to on-chip memories and peripherals are
considered "Reserved"). For the detailed mapping of available memory and register areas,
please refer to the
chapters.
2.2.2

Memory map and register boundary addresses

The following table gives the memory map and boundary addresses of the peripherals
available in all STM32F05xxx devices.
Table 2. STM32F05xxx memory map and peripheral register boundary addresses
Bus Boundary address
0xE000 0000 - 0xE00F FFFF 1MB
0x4800 1800 - 0x5FFF FFFF
0x4800 1400 - 0x4800 17FF
0x4800 1000 - 0x4800 13FF
0x4800 0C00 - 0x4800 0FFF
AHB2
0x4800 0800 - 0x4800 0BFF
0x4800 0400 - 0x4800 07FF
0x4800 0000 - 0x4800 03FF
0x4002 4400 - 0x47FF FFFF
0x4002 4000 - 0x4002 43FF
0x4002 3400 - 0x4002 3FFF
0x4002 3000 - 0x4002 33FF
0x4002 2400 - 0x4002 2FFF
AHB1 0x4002 2000 - 0x4002 23FF
0x4002 1400 - 0x4002 1FFF
0x4002 1000 - 0x4002 13FF
0x4002 0400 - 0x4002 0FFF
0x4002 0000 - 0x4002 03FF
0x4001 8000 - 0x4001 FFFF
Memory map and register boundary addresses
Size
Cortex M0 internal
peripherals
~384 MB Reserved
1KB GPIOF
1KB Reserved
1KB GPIOD
1KB GPIOC
1KB GPIOB
1KB GPIOA
~128 MB Reserved
1 KB TSC
3 KB Reserved
1 KB CRC
3 KB Reserved
1 KB FLASH interface
3 KB Reserved
1 KB RCC
3 KB Reserved
1 KB DMA
32 KB Reserved
Doc ID 018940 Rev 1
Peripheral
Section 8.4.11 on page 133
Section 8.4.11 on page 133
Section 8.4.11 on page 133
Section 8.4.11 on page 133
Section 8.4.11 on page 133
Section 27.6.11 on page 697
Section 5.4.5 on page 66
Section 3.6 on page 58
Section 7.4.15 on page 116
Section 10.4.7 on page 155
chapter and peripheral
Peripheral register map
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