STMicroelectronics SPC572L series Reference Manual page 1183

RM0400
46.5.2.4.2 Draining the TX FIFO
The TX FIFO entries are removed (drained) by shifting SPI data out through the shift
register. Entries are transferred from the TX FIFO to the shift register and shifted out as long
as there are valid entries in the TX FIFO. Every time an entry is transferred from the TX
FIFO to the shift register, the TX FIFO Counter decrements by one.
When Extended SPI Mode (DSPI_MCR[XSPI]) is enabled and the frame size of SPI Data to
be transmitted is more than 16 bits, then two Data entries are popped from TX FIFO
simultaneously and transferred to the shift register. The first of the two popped entries forms
the 16 LSB bits of the SPI frame. Such an operation also causes TX FIFO Counter to
decrement by two.
At the end of a transfer, the TCF bit in the SR is set to indicate the completion of a transfer.
The TX FIFO is flushed by writing a '1' to the CLR_TXF bit in MCR.
If an external bus master initiates a transfer with a DSPI slave while the slave's DSPI TX
FIFO is empty, the Transmit FIFO Underflow Flag (TFUF) in the slave's SR is set. See
Section 46.5.12.9: Transmit FIFO Underflow interrupt request
46.5.2.5 Command First In First Out (CMD FIFO) buffering mechanism
The CMD FIFO functions as a buffer of SPI command used for SPI data transmission.
The CMD FIFO holds four entries, each representing command fields. The number of
entries in the CMD FIFO is device-specific.
SPI Command is added to the CMD FIFO by writing to the command field of DSPI PUSH
FIFO Register (PUSHR). CMD FIFO entries can only be removed from the CMD FIFO by
being shifted out (to help transmit SPI data) or by flushing the CMD FIFO.
When Extended SPI Mode (DSPI_MCR[XSPI]) is disabled:
•
The TX FIFO and CMD FIFO must be filled together as every CMDFIFO entry has a
corresponding single TXFIFO entry attached to it.
When Extended SPI Mode (DSPI_MCR[XSPI]) is enabled:
• The TX FIFO and CMD FIFO can be filled independently as every CMDFIFO entry can
have multiple TXFIFO entries attached to it.
•
The CTARE[DTCP] field decides the number of SPI Data Frames of size {FMSZE,
FMSZ} to be transmitted using the current Command Entry. FMSZ and FMSZE fields
are given in the CTAR/CTARE registers respectively, pointed by the CTAS field in the
Command frame.
•
The amount of time a command entry is in use is known as a Command Cycle. The
Busy flag DSPI_SR[BSYF] is asserted for the duration of the Command Cycle except
for the last SPI frame in the Command Cycle.
The CMD FIFO Counter field (CMDCTR) in the DSPI Status Register (SR) indicates the
number of valid entries in the CMD FIFO. The TXCTR is updated every time an 8 or 16-bit
write takes place on the lower half of DSPI_PUSHR or SPI data is transferred into the shift
register from the TX FIFO.
The CMDNXTPTR field indicates which CMD FIFO entry is used during the next command
cycle. This field is incremented every time the last SPI data in the command cycle is
transferred from the TX FIFO to the shift register. The maximum value of the field is equal to
the maximum implemented TXFR register number and it rolls over after reaching the
maximum.
Deserial Serial Peripheral Interface (DSPI)
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