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STMicroelectronics STM32WLEx Wireless Manuals
Manuals and User Guides for STMicroelectronics STM32WLEx Wireless. We have
1
STMicroelectronics STM32WLEx Wireless manual available for free PDF download: Reference Manual
STMicroelectronics STM32WLEx Reference Manual (1306 pages)
Advanced Arm-based 32-bit MCUs with sub-GHz Radio Solution
Brand:
STMicroelectronics
| Category:
Microcontrollers
| Size: 26 MB
Table of Contents
Table of Contents
2
Sub-Ghz Radio Generic Synchronization Word Control Register
4
Sub-Ghz Radio Generic Synchronization Word Control Register
5
Sub-Ghz Radio Generic Synchronization Word Control Register
6
List of Tables
41
Documentation Conventions
55
General Information
55
List of Abbreviations for Registers
55
Availability of Peripherals
56
Glossary
56
Memory and Bus Architecture
57
System Architecture
57
Figure 1. System Architecture
58
S0: CPU I-Bus
58
S1: CPU D-Bus
58
S2: CPU S-Bus
58
Boot Configuration
59
S4, S5: DMA-Bus
59
Table 1. Device Boot Mode
59
SRAM Erase
61
Table 2. SRAM Erase Conditions
61
Introduction
62
Memory Organization
62
Figure 2. Memory Map
63
Memory Map and Register Boundary Addresses
63
Table 3. Memory Map and Peripheral Register Boundary Addresses
64
CPU Bit Banding
67
Embedded Flash Memory (FLASH)
69
FLASH Functional Description
69
FLASH Introduction
69
FLASH Main Features
69
Flash Memory Organization
69
Empty Check
70
Table 4. Flash Memory - Single Bank Organization
70
Error Code Correction (ECC)
71
Read Access Latency
71
Adaptive Real-Time Memory Accelerator (ART Accelerator)
72
Table 5. Number of Wait States According to Flash Clock (HCLK3) Frequency
72
Figure 3. Sequential 16 Bits Instructions Execution
74
Flash Program and Erase Operations
75
Flash Main Memory Erase Sequences
76
Table 6. Page Erase Overview
76
Flash Main Memory Programming Sequences
77
Table 7. Mass Erase Overview
77
Table 8. Errors in Page-Based Row Programming
81
FLASH Option Bytes
82
Option Bytes Description
82
Option Bytes Programming
83
Table 9. Option Bytes Organization
83
Flash Memory Protection
85
Table 10. Option Loading Control
85
Readout Protection (RDP)
86
Table 11. Flash Memory Readout Protection Status
86
Table 12. RDP Regression from Level 1 to Level 0 and Memory Erase
87
Figure 4. Changing the RDP Level
88
Table 13. Access Status Versus Protection Level and Execution Modes
88
Proprietary Code Readout Protection (PCROP)
89
Write Protection (WRP)
90
CPU Boot Lock Chain of Trust
91
FLASH Program Erase Suspension
91
Security (ESE)
91
FLASH Access Control Register (FLASH_ACR)
92
FLASH Interrupts
92
FLASH Registers
92
Table 16. Flash Interrupt Requests
92
FLASH Key Register (FLASH_KEYR)
94
FLASH Option Key Register (FLASH_OPTKEYR)
94
FLASH Status Register (FLASH_SR)
95
FLASH Control Register (FLASH_CR)
97
FLASH ECC Register (FLASH_ECCR)
99
FLASH Option Register (FLASH_OPTR)
100
FLASH PCROP Zone a Start Address Register (FLASH_PCROP1ASR)
102
FLASH PCROP Zone a End Address Register (FLASH_PCROP1AER)
103
FLASH WRP Area a Address Register (FLASH_WRP1AR)
104
FLASH WRP Area B Address Register (FLASH_WRP1BR)
104
FLASH PCROP Zone B End Address Register (FLASH_PCROP1BER)
105
FLASH PCROP Zone B Start Address Register (FLASH_PCROP1BSR)
105
FLASH Register Map
107
Table 17. Flash Interface Register Map and Reset Values
107
Sub-Ghz Radio (SUBGHZ)
109
Sub-Ghz Radio Introduction
109
Sub-Ghz Radio Main Features
109
Figure 5. Sub-Ghz Radio System Block Diagram
110
General Description
110
Sub-Ghz Radio Functional Description
110
Sub-Ghz Radio Signals
110
Table 18. Sub-Ghz Internal Input/Output Signals
110
Figure 6. High Output Power PA
111
Transmitter
111
Figure 7. Low Output Power PA
112
Receiver
112
Table 19. Sub-Ghz Radio Transmit High Output Power
112
Intermediate Frequencies
113
Rf-Pll
113
Table 20. FSK Mode Intermediate Frequencies
113
HSE32 Reference Clock
114
Internal Oscillators
114
Sub-Ghz Radio Clocks
114
Table 21. Lora Mode Intermediate Frequencies
114
Lora Modem
115
Sub-Ghz Radio Modems
115
Table 22. Spreading Factor, Chips/Symbol and Lora SNR
116
Table 23. Lora Bandwidth Setting
116
Lora Framing
117
Table 24. Coding Rate and Overhead Ratio
117
Figure 8. Lora Packet Frames Format
118
FSK Modem
119
Generic Framing
120
MSK Modem
120
Figure 9. Generic Packet Frames Format
121
BPSK Modem
122
BPSK Framing
123
Figure 10. Sub-Ghz RAM Data Buffer Operation
123
Sub-Ghz Radio Data Buffer
123
Receive Data Buffer Operation
124
Sub-Ghz Radio Operating Modes
124
Transmit Data Buffer Operation
124
Figure 11. Sub-Ghz Radio Operating Modes
125
Calibration Mode
126
Sleep Mode
126
Startup Mode
126
Frequency Synthesis Mode (FS)
127
Standby Mode
127
Transmit Mode (TX)
127
Active Mode Switching Time
128
Receive Mode (RX)
128
Figure 12. Sub-Ghz Radio BUSY Timing
129
Sub-Ghz Radio SPI Interface
129
Table 25. Operation Mode Transition BUSY Switching Time
129
Register and Buffer Access Commands
130
Sub-Ghz Radio Command Structure
130
Table 26. Command Structure
130
Operating Mode Commands
132
Figure 13. Receiver Listening Mode Timing
135
Sub-Ghz Radio Configuration Commands
137
Table 27. PA Optimal Setting and Operating Modes
139
Table 28. Recommended CAD Configuration Settings
141
Communication Status Information Commands
148
IRQ Interrupt Commands
151
Table 29. IRQ Bit Mapping and Definition
151
Miscellaneous Commands
153
Table 30. Image Calibration for ISM Bands
154
Set_Tcxomode Command
156
Table 31. Command Format Set_Tcxomode()
156
Sub-Ghz Radio Commands Overview
157
Table 32. Regtcxotrim and Timeout Bytes Definition
157
Table 33. Sub-Ghz Radio SPI Commands Overview
157
Basic Sequence for Lora, (G)MSK and (G)FSK Transmit Operation
159
Sub-Ghz Radio Application Configuration
159
Basic Sequence for Lora and (G)FSK Receive Operation
160
Basic Sequence for BPSK Transmit Operation
161
Sub-Ghz Radio Ramp-Up MSB Register (SUBGHZ_RAM_RAMPUPH)
161
Sub-Ghz Radio Registers
161
Sub-Ghz Radio Frame Limit MSB Register
162
Sub-Ghz Radio Ramp-Down LSB Register
162
Sub-Ghz Radio Ramp-Down MSB Register
162
Sub-Ghz Radio Ramp-Up LSB Register (SUBGHZ_RAM_RAMPUPL)
162
Sub-Ghz Radio Frame Limit LSB Register (SUBGHZ_RAM_FRAMELIML)
163
Sub-Ghz Radio Generic Bit Synchronization Register (SUBGHZ_GBSYNCR)
163
Sub-Ghz Radio Generic CFO MSB Register (SUBGHZ_GCFORH)
163
(Subghz_Gpktctl1Ar)
164
(Subghz_Gpktctl1R)
164
Sub-Ghz Radio Generic CFO LSB Register (SUBGHZ_GCFORL)
164
Sub-Ghz Radio Generic Packet Control 1 Register
164
Sub-Ghz Radio Generic Packet Control 1A Register
164
(Subghz_Gcrcinirh)
165
(Subghz_Grtxpldlen)
165
(Subghz_Gwhiteinirl)
165
Sub-Ghz Radio Generic CRC Initial MSB Register
165
Sub-Ghz Radio Generic Payload Length Register
165
Sub-Ghz Radio Generic Whitening LSB Register
165
(Subghz_Gcrcinirl)
166
(Subghz_Gcrcpolrh)
166
(Subghz_Gcrcpolrl)
166
Sub-Ghz Radio Generic CRC Initial LSB Register
166
Sub-Ghz Radio Generic CRC Polynomial LSB Register
166
Sub-Ghz Radio Generic CRC Polynomial MSB Register
166
(Subghz_Gsyncr4)
167
(Subghz_Gsyncr5)
167
(Subghz_Gsyncr6)
167
(Subghz_Gsyncr7)
167
Sub-Ghz Radio Generic Synchronization Word Control Register 7
167
(Subghz_Paocpr)
175
Sub-Ghz Radio Disable Mixer Register (REG_ANA_MIXER)
175
Sub-Ghz Radio PA over Current Protection Register
175
Sub-Ghz Radio RTC Control Register (SUBGHZ_RTCCTLR)
175
(Subghz_Rtcprdr1)
176
Sub-Ghz Radio RTC Period LSB Register (SUBGHZ_RTCPRDR0)
176
Sub-Ghz Radio RTC Period MID-Byte Register
176
Sub-Ghz Radio RTC Period MSB Register (SUBGHZ_RTCPRDR2)
176
(Subghz_Hseintrimr)
177
(Subghz_Hseouttrimr)
177
Sub-Ghz Radio HSE32 OSC_IN Capacitor Trim Register
177
Sub-Ghz Radio HSE32 OSC_OUT Capacitor Trim Register
177
Sub-Ghz Radio Power Control Register (SUBGHZ_PCR)
178
Sub-Ghz Radio SMPS Control 0 Register (SUBGHZ_SMPSC0R)
178
Sub-Ghz Radio SMPS Control 2 Register (SUBGHZ_SMPSC2R)
178
Sub-Ghz Radio Register Map
179
Sub-Ghz Radio RTC Control Register (SUBGHZ_EVENTMASKR)
179
Table 34. SUBGHZ Register Map and Reset Values
179
Power Control (PWR)
182
Power Supplies
182
Figure 14. Power Supply Overview
183
Figure 15. Supply Configurations
184
Battery Backup Domain
185
Independent Analog Peripherals Supply
185
Dynamic Voltage Scaling Management
187
Voltage Regulator
187
Brownout Reset (BOR)
188
Power Supply Supervisor
188
Power-On Reset (Por)/Power-Down Reset (PDR)
188
Figure 16. Brownout Reset Waveform
189
Programmable Voltage Detector (PVD)
189
Figure 17. PVD Thresholds
190
Peripheral Voltage Monitoring (PVM)
190
Table 35. PVM Features
190
Figure 18. EOL Thresholds
191
Radio Busy Management
191
Radio End of Life (EOL)
191
Figure 19. Radio Busy Management
192
Low-Power Modes
193
Table 36. Low-Power Mode Summary
194
Table 37. Functionalities Depending on System Operating Mode
195
Table 38. MCU and Sub-Ghz Radio Operating Modes
198
Low-Power Run Mode (Lprun)
199
Run Mode
199
Enter Low-Power Mode
200
Exit Low-Power Mode
200
Table 39. Lprun
200
Sleep Mode
201
Table 40. CPU Wakeup Versus System Operating Mode
201
Low-Power Sleep Mode (Lpsleep)
202
Table 41. Sleep Mode
202
Stop 0 Mode
203
Table 42. Lpsleep
203
Stop 1 Mode
205
Table 43. Stop 0 Mode
205
Stop 2 Mode
206
Table 44. Stop 1 Mode
206
Standby Mode
208
Table 45. Stop 2 Mode
208
Shutdown Mode
210
Table 46. Standby Mode
210
Auto-Wakeup from Low-Power Mode
211
Table 47. Shutdown Mode
211
PWR Control Register 1 (PWR_CR1)
212
PWR Registers
212
PWR Control Register 2 (PWR_CR2)
214
PWR Control Register 3 (PWR_CR3)
215
PWR Control Register 4 (PWR_CR4)
217
PWR Status Register 1 (PWR_SR1)
218
Power Status Register 2 (PWR_SR2)
219
PWR Status Clear Register (PWR_SCR)
221
PWR Control Register 5 (PWR_CR5)
222
PWR Port a Pull-Up Control Register (PWR_PUCRA)
222
PWR Port a Pull-Down Control Register (PWR_PDCRA)
223
PWR Port B Pull-Up Control Register (PWR_PUCRB)
223
PWR Port B Pull-Down Control Register (PWR_PDCRB)
224
PWR Port C Pull-Up Control Register (PWR_PUCRC)
224
PWR Port C Pull-Down Control Register (PWR_PDCRC)
225
PWR Port H Pull-Up Control Register (PWR_PUCRH)
225
PWR Extended Status and Status Clear Register (PWR_EXTSCR)
226
PWR Port H Pull-Down Control Register (PWR_PDCRH)
226
PWR Sub-Ghz SPI Control Register (PWR_SUBGHZSPICR)
227
PWR Register Map
228
Table 48. PWR Register Map and Reset Values
228
Power Reset
230
Reset
230
Reset and Clock Control (RCC)
230
System Reset
230
Backup Domain Reset
231
Figure 20. Simplified Diagram of the Reset Circuit
231
Clocks
232
PKA SRAM Reset
232
Sub-Ghz Radio Reset
232
Figure 21. Clock Tree
234
HSE32 Clock with Trimming
234
Figure 22. HSE32 Clock Sources
236
Figure 23. HSE32 TCXO Control
237
HSI16 Clock
237
Figure 24. LSE Clock Sources
240
Table 49. Clock Source Stabilization Times
241
Table 50. Clock Source Frequency
242
Table 51. SPI2S2 I2S Clock PLL Configurations
243
Table 52. Sub-Ghz Radio SPI Clock Configurations
243
Figure 25. Frequency Measurement with TIM16 in Capture Mode
246
Figure 26. Frequency Measurement with TIM17 in Capture Mode
246
Table 53. Peripheral Clock Enable
248
Table 54. Low-Power Debug Configurations
249
Table 55. RCC Register Map and Reset Values
292
Figure 27. HSEM Block Diagram
297
Table 56. HSEM Internal Input/Output Signals
297
Figure 28. Procedure State Diagram
298
Figure 29. Interrupt State Diagram
301
Table 57. Authorized AHB Bus Master ID
302
Table 58. HSEM Register Map and Reset Values
308
Figure 30. Basic Structure of a Standard I/O Port Bit
310
Figure 31. Basic Structure of a 5V-Tolerant I/O Port Bit
311
Table 59. Port Bit Configurations
311
Figure 32. Input Floating/Pull-Up/Pull-Down Configurations
315
Figure 33. Output Configuration
316
Figure 34. Alternate Function Configuration
316
Figure 35. High Impedance Analog Configuration
317
Table 60. GPIOA Register Map and Reset Values
337
Table 61. GPIOB Register Map and Reset Values
338
Table 62. GPIOC Register Map and Reset Values
339
Table 63. GPIOH Register Map and Reset Values
340
Table 64. SYSCFG Register Map and Reset Values
349
Table 65. Stm32Wlex Peripherals Interconnect Matrix
351
Table 66. DMA1 and DMA2 Implementation
360
Figure 36. DMA Block Diagram
361
Table 67. DMA Internal Input/Output Signals
362
Table 68. Programmable Data Width and Endian Behavior (When PINC = MINC = 1)
368
Table 69. DMA Interrupt Requests
370
Table 70. DMA Register Map and Reset Values
379
Table 71. DMAMUX Instantiation
383
Table 72. DMAMUX1: Assignment of Multiplexer Inputs to Resources
384
Table 73. DMAMUX1: Assignment of Trigger Inputs to Resources
384
Table 74. DMAMUX1: Assignment of Synchronization Inputs to Resources
385
Figure 37. DMAMUX Block Diagram
386
Table 75. DMAMUX Signals
387
Figure 38. Synchronization Mode of the DMAMUX Request Line Multiplexer Channel
389
Figure 39. Event Generation of the DMA Request Line Multiplexer Channel
390
Table 76. DMAMUX Interrupts
392
Table 77. DMAMUX Register Map and Reset Values
398
Table 78. Vector Table
400
Figure 40. EXTI Block Diagram
404
Table 79. EXTI Pin Overview
404
Table 80. EVG Pin Overview
404
Table 81. Wakeup Interrupts
405
Exti Functional Description
407
Table 82. EXTI Event Input Configurations and Register Control
407
Figure 41. Configurable Event Trigger Logic CPU Wakeup
408
Figure 42. Direct Event Trigger Logic CPU Wakeup
409
Table 83. Masking Functionality
409
EXTI Rising Trigger Selection Register (EXTI_RTSR1)
410
Table 84. EXTI Register Map Sections
410
EXTI Rising Trigger Selection Register (EXTI_RTSR2)
414
EXTI Falling Trigger Selection Register (EXTI_FTSR2)
415
EXTI Software Interrupt Event Register (EXTI_SWIER2)
415
EXTI Interrupt Mask Register (EXTI_IMR1)
416
EXTI Pending Register (EXTI_PR2)
416
EXTI Event Mask Register (EXTI_EMR1)
417
Table 85. EXTI Register Map and Reset Values
418
Figure 43. CRC Calculation Unit Block Diagram
421
Table 86. CRC Internal Input/Output Signals
421
Table 87. CRC Register Map and Reset Values
426
Figure 44. ADC Block Diagram
429
Table 88. ADC Input/Output Pins
429
Table 89. ADC Internal Input/Output Signals
430
Table 90. External Triggers
430
Figure 45. ADC Calibration
432
Figure 46. Calibration Factor Forcing
432
Figure 47. Enabling/Disabling the ADC
433
Figure 48. ADC Clock Scheme
434
Table 91. Latency between Trigger and Start of Conversion
435
Figure 49. ADC Connectivity
436
Figure 50. Analog to Digital Conversion Time
441
Figure 51. ADC Conversion Timings
441
Figure 52. Stopping an Ongoing Conversion
442
Table 92. Configuring the Trigger Polarity
442
Table 93. Tsar Timings Depending on Resolution
444
Figure 53. Single Conversions of a Sequence, Software Trigger
445
Figure 54. Continuous Conversion of a Sequence, Software Trigger
445
Figure 55. Single Conversions of a Sequence, Hardware Trigger
446
Figure 56. Continuous Conversions of a Sequence, Hardware Trigger
446
Figure 57. Data Alignment and Resolution (Oversampling Disabled: OVSE = 0)
447
Figure 58. Example of Overrun (OVR)
448
Figure 59. Wait Mode Conversion (Continuous Mode, Software Trigger)
451
Figure 60. Behavior with WAIT = 0, AUTOFF = 1
452
Figure 62. Analog Watchdog Guarded Area
453
Table 94. Analog Watchdog Comparison
453
Table 95. Analog Watchdog 1 Channel Selection
453
Figure 63. Adc_Awdx_Out Signal Generation
455
Figure 64. Adc_Awdx_Out Signal Generation (Awdx Flag Not Cleared by Software)
455
Figure 65. Adc_Awdx_Out Signal Generation (on a Single Channel)
456
Figure 66. Analog Watchdog Threshold Update
456
Figure 67. 20-Bit to 16-Bit Result Truncation
457
Figure 68. Numerical Example with 5-Bits Shift and Rounding
458
Table 96. Maximum Output Results Vs N and M. Grayed Values Indicates Truncation
458
Figure 69. Triggered Oversampling Mode (TOVS Bit = 1)
460
Figure 70. Temperature Sensor and VREFINT Channel Block Diagram
461
Figure 71. VBAT Channel Block Diagram
463
Table 97. ADC Interrupts
463
Table 98. ADC Register Map and Reset Values
484
Figure 72. DAC Block Diagram
488
Table 99. DAC Features
488
Table 100. DAC Input/Output Pins
489
Table 101. DAC Internal Input/Output Signals
489
Table 102. DAC Interconnection
489
Figure 73. Data Registers in Single DAC Channel Mode
490
Figure 74. Timing Diagram for Conversion with Trigger Disabled TEN = 0
491
Figure 75. DAC LFSR Register Calculation Algorithm
493
Figure 76. DAC Conversion (SW Trigger Enabled) with LFSR Wave Generation
493
Figure 77. DAC Triangle Wave Generation
494
Figure 78. DAC Conversion (SW Trigger Enabled) with Triangle Wave Generation
494
Table 103. Sample and Refresh Timings
496
Figure 79. DAC Sample and Hold Mode Phase Diagram
497
Table 104. Channel Output Modes Summary
497
Table 105. Effect of Low-Power Modes on DAC
500
Table 106. DAC Interrupts
501
Table 107. DAC Register Map and Reset Values
511
Table 108. VREF Buffer Modes
513
Table 109. VREFBUF Register Map and Reset Values
515
Figure 80. Comparator Block Diagram
517
Table 110. COMP1 Input Plus Assignment
517
Table 111. COMP1 Input Minus Assignment
518
Table 112. COMP2 Input Plus Assignment
518
Table 113. COMP2 Input Minus Assignment
518
Figure 81. Window Mode
520
Figure 82. Comparator Hysteresis
520
Figure 83. Comparator Output Blanking
521
Table 114. Comparator Behavior in the Low-Power Modes
522
Table 115. Interrupt Control Bits
522
Table 116. COMP Register Map and Reset Values
527
Figure 84. RNG Block Diagram
529
Table 117. RNG Internal Input/Output Signals
529
Figure 85. NIST SP800-90B Entropy Source Model
530
Figure 86. RNG Initialization Overview
533
Table 118. RNG Interrupt Requests
537
Table 119. RNG Configurations
538
Table 120. RNG Register Map and Reset Map
543
Figure 87. AES Block Diagram
545
Table 121. AES Internal Input/Output Signals
545
Figure 88. ECB Encryption and Decryption Principle
547
Figure 89. CBC Encryption and Decryption Principle
548
Figure 90. CTR Encryption and Decryption Principle
549
Figure 91. GCM Encryption and Authentication Principle
550
Figure 92. GMAC Authentication Principle
550
Figure 93. CCM Encryption and Authentication Principle
551
Figure 94. Example of Suspend Mode Management
555
Figure 95. ECB Encryption
556
Figure 96. ECB Decryption
556
Figure 97. CBC Encryption
557
Figure 98. CBC Decryption
557
Figure 99. ECB/CBC Encryption (Mode 1)
558
Figure 100. ECB/CBC Decryption (Mode 3)
559
Figure 101. Message Construction in CTR Mode
560
Figure 102. CTR Encryption
561
Figure 103. CTR Decryption
561
Table 122. CTR Mode Initialization Vector Definition
561
Figure 104. Message Construction in GCM
563
Table 123. GCM Last Block Definition
563
Figure 105. GCM Authenticated Encryption
564
Table 124. Initialization of Aes_Ivrx Registers in GCM Mode
564
Figure 106. Message Construction in GMAC Mode
568
Figure 107. GMAC Authentication Mode
568
Figure 108. Message Construction in CCM Mode
569
Figure 109. CCM Mode Authenticated Encryption
571
Table 125. Initialization of Aes_Ivrx Registers in CCM Mode
571
Figure 110. 128-Bit Block Construction with Respect to Data Swap
575
Table 126. Key Endianness in Aes_Keyrx Registers (128- or 256-Bit Key Length)
576
Figure 111. DMA Transfer of a 128-Bit Data Block During Input Phase
577
Figure 112. DMA Transfer of a 128-Bit Data Block During Output Phase
578
Table 127. AES Interrupt Requests
579
Table 128. Processing Latency for ECB, CBC and CTR
579
Table 129. Processing Latency for GCM and CCM (in Clock Cycles)
580
Table 130. AES Register Map and Reset Values
590
Figure 113. PKA Block Diagram
593
Table 131. Internal Input/Output Signals
593
Table 132. PKA Integer Arithmetic Functions List
594
Table 133. PKA Prime Field (Fp) Elliptic Curve Functions List
594
Table 134. Montgomery Parameter Computation
599
Table 135. Modular Addition
600
Table 136. Modular Subtraction
600
Table 137. Montgomery Multiplication
601
Table 138. Modular Exponentiation (Normal Mode)
602
Table 139. Modular Exponentiation (Fast Mode)
602
Table 140. Modular Inversion
602
Table 141. Modular Reduction
603
Table 142. Arithmetic Addition
603
Table 143. Arithmetic Subtraction
603
Table 144. Arithmetic Multiplication
604
Table 145. Arithmetic Comparison
604
Table 146. CRT Exponentiation
605
Table 147. Point on Elliptic Curve Fp Check
606
Table 148. ECC Fp Scalar Multiplication
606
Table 149. ECC Fp Scalar Multiplication (Fast Mode)
607
Table 150. ECDSA Sign - Inputs
608
Table 151. ECDSA Sign - Outputs
608
Table 152. Extended ECDSA Sign (Extra Outputs)
609
Table 153. ECDSA Verification (Inputs)
609
Table 154. ECDSA Verification (Outputs)
609
Table 155. Family of Supported Curves for ECC Operations
610
Table 156. Modular Exponentiation Computation Times
612
Table 157. ECC Scalar Multiplication Computation Times
612
Table 158. ECDSA Signature Average Computation Times
612
Table 159. ECDSA Verification Average Computation Times
613
Table 160. Point on Elliptic Curve Fp Check Average Computation Times
613
Table 161. Montgomery Parameters Average Computation Times
613
Table 162. PKA Interrupt Requests
613
Table 163. PKA Register Map and Reset Values
617
Figure 114. Advanced-Control Timer Block Diagram
620
Figure 115. Counter Timing Diagram with Prescaler Division Change from 1 to 2
622
Figure 116. Counter Timing Diagram with Prescaler Division Change from 1 to 4
622
Figure 117. Counter Timing Diagram, Internal Clock Divided by 1
624
Figure 118. Counter Timing Diagram, Internal Clock Divided by 2
624
Figure 119. Counter Timing Diagram, Internal Clock Divided by 4
625
Figure 120. Counter Timing Diagram, Internal Clock Divided by N
625
Figure 121. Counter Timing Diagram, Update Event When ARPE=0 (Timx_Arr Not Preloaded)
626
Figure 122. Counter Timing Diagram, Update Event When ARPE=1 (Timx_Arr Preloaded)
626
Figure 123. Counter Timing Diagram, Internal Clock Divided by 1
628
Figure 124. Counter Timing Diagram, Internal Clock Divided by 2
628
Figure 125. Counter Timing Diagram, Internal Clock Divided by 4
629
Figure 126. Counter Timing Diagram, Internal Clock Divided by N
629
Figure 127. Counter Timing Diagram, Update Event When Repetition Counter Is Not Used
630
Figure 128. Counter Timing Diagram, Internal Clock Divided by 1, Timx_Arr = 0X6
631
Figure 129. Counter Timing Diagram, Internal Clock Divided by 2
632
Figure 130. Counter Timing Diagram, Internal Clock Divided by 4, Timx_Arr=0X36
632
Figure 131. Counter Timing Diagram, Internal Clock Divided by N
633
Figure 132. Counter Timing Diagram, Update Event with ARPE=1 (Counter Underflow)
633
Figure 133. Counter Timing Diagram, Update Event with ARPE=1 (Counter Overflow)
634
Figure 134. Update Rate Examples Depending on Mode and Timx_Rcr Register Settings
635
Figure 135. External Trigger Input Block
636
Figure 137. Control Circuit in Normal Mode, Internal Clock Divided by 1
637
Figure 138. TI2 External Clock Connection Example
638
Figure 139. Control Circuit in External Clock Mode 1
639
Figure 140. External Trigger Input Block
639
Figure 141. Control Circuit in External Clock Mode 2
640
Figure 142. Capture/Compare Channel (Example: Channel 1 Input Stage)
641
Figure 143. Capture/Compare Channel 1 Main Circuit
641
Figure 144. Output Stage of Capture/Compare Channel (Channel 1, Idem Ch. 2 and 3)
642
Figure 145. Output Stage of Capture/Compare Channel (Channel 4)
642
Figure 146. Output Stage of Capture/Compare Channel (Channel 5, Idem Ch. 6)
643
Figure 147. PWM Input Mode Timing
645
Figure 148. Output Compare Mode, Toggle on OC1
647
Figure 149. Edge-Aligned PWM Waveforms (ARR=8)
648
Figure 150. Center-Aligned PWM Waveforms (ARR=8)
649
Figure 151. Generation of 2 Phase-Shifted PWM Signals with 50% Duty Cycle
651
Figure 152. Combined PWM Mode on Channel 1 and 3
652
Figure 153. 3-Phase Combined PWM Signals with Multiple Trigger Pulses Per Period
653
Figure 154. Complementary Output with Dead-Time Insertion
654
Figure 155. Dead-Time Waveforms with Delay Greater than the Negative Pulse
654
Figure 156. Dead-Time Waveforms with Delay Greater than the Positive Pulse
655
Figure 157. Break and Break2 Circuitry Overview
657
Figure 158. Various Output Behavior in Response to a Break Event on BRK (OSSI = 1)
659
Figure 159. PWM Output State Following BRK and BRK2 Pins Assertion (OSSI=1)
660
Table 164. Behavior of Timer Outputs Versus BRK/BRK2 Inputs
660
Figure 160. PWM Output State Following BRK Assertion (OSSI=0)
661
Figure 161. Output Redirection (BRK2 Request Not Represented)
662
Table 165. Break Protection Disarming Conditions
662
Figure 162. Clearing Timx Ocxref
663
Figure 163. 6-Step Generation, COM Example (OSSR=1)
664
Figure 164. Example of One Pulse Mode
665
Figure 165. Retriggerable One Pulse Mode
667
Figure 166. Example of Counter Operation in Encoder Interface Mode
668
Table 166. Counting Direction Versus Encoder Signals
668
Figure 167. Example of Encoder Interface Mode with TI1FP1 Polarity Inverted
669
Figure 168. Measuring Time Interval between Edges on 3 Signals
670
Figure 169. Example of Hall Sensor Interface
672
Figure 170. Control Circuit in Reset Mode
673
Figure 171. Control Circuit in Gated Mode
674
Figure 172. Control Circuit in Trigger Mode
675
Figure 173. Control Circuit in External Clock Mode 2 + Trigger Mode
676
Table 167. TIM1 Internal Trigger Connection
685
Table 168. Output Control Bits for Complementary Ocx and Ocxn Channels with Break Feature
699
Table 169. TIM1 Register Map and Reset Values
716
Figure 174. General-Purpose Timer Block Diagram
720
Figure 175. Counter Timing Diagram with Prescaler Division Change from 1 to 2
722
Figure 176. Counter Timing Diagram with Prescaler Division Change from 1 to 4
722
Figure 177. Counter Timing Diagram, Internal Clock Divided by 1
723
Figure 178. Counter Timing Diagram, Internal Clock Divided by 2
724
Figure 179. Counter Timing Diagram, Internal Clock Divided by 4
724
Figure 180. Counter Timing Diagram, Internal Clock Divided by N
725
Figure 181. Counter Timing Diagram, Update Event When ARPE=0 (Timx_Arr Not Preloaded)
725
Figure 182. Counter Timing Diagram, Update Event When ARPE=1 (Timx_Arr Preloaded)
726
Figure 183. Counter Timing Diagram, Internal Clock Divided by 1
727
Figure 184. Counter Timing Diagram, Internal Clock Divided by 2
727
Figure 185. Counter Timing Diagram, Internal Clock Divided by 4
728
Figure 186. Counter Timing Diagram, Internal Clock Divided by N
728
Figure 187. Counter Timing Diagram, Update Event When Repetition Counter
729
Is Not Used
729
Figure 188. Counter Timing Diagram, Internal Clock Divided by 1, Timx_Arr=0X6
730
Figure 189. Counter Timing Diagram, Internal Clock Divided by 2
731
Figure 190. Counter Timing Diagram, Internal Clock Divided by 4, Timx_Arr=0X36
731
Figure 191. Counter Timing Diagram, Internal Clock Divided by N
732
Figure 192. Counter Timing Diagram, Update Event with ARPE=1 (Counter Underflow)
732
Figure 193. Counter Timing Diagram, Update Event with ARPE=1 (Counter Overflow)
733
Figure 194. Control Circuit in Normal Mode, Internal Clock Divided by 1
734
Figure 195. TI2 External Clock Connection Example
734
Figure 196. Control Circuit in External Clock Mode 1
735
Figure 197. External Trigger Input Block
736
Figure 198. Control Circuit in External Clock Mode 2
737
Figure 199. Capture/Compare Channel (Example: Channel 1 Input Stage)
737
Figure 200. Capture/Compare Channel 1 Main Circuit
738
Figure 201. Output Stage of Capture/Compare Channel (Channel 1)
738
Figure 202. PWM Input Mode Timing
740
Figure 203. Output Compare Mode, Toggle on OC1
742
Figure 204. Edge-Aligned PWM Waveforms (ARR=8)
743
Figure 205. Center-Aligned PWM Waveforms (ARR=8)
745
Figure 206. Generation of 2 Phase-Shifted PWM Signals with 50% Duty Cycle
746
Figure 207. Combined PWM Mode on Channels 1 and 3
747
Figure 208. Clearing Timx Ocxref
748
Figure 209. Example of One-Pulse Mode
749
Figure 210. Retriggerable One-Pulse Mode
751
Figure 211. Example of Counter Operation in Encoder Interface Mode
752
Table 170. Counting Direction Versus Encoder Signals
752
Figure 212. Example of Encoder Interface Mode with TI1FP1 Polarity Inverted
753
Figure 213. Control Circuit in Reset Mode
754
Figure 214. Control Circuit in Gated Mode
755
Figure 215. Control Circuit in Trigger Mode
756
Figure 216. Control Circuit in External Clock Mode 2 + Trigger Mode
757
Figure 217. Master/Slave Timer Example
757
Figure 218. Master/Slave Connection Example with 1 Channel Only Timers
758
Figure 219. Gating TIM2 with OC1REF of TIM1
759
Figure 220. Gating TIM2 with Enable of TIM1
760
Figure 221. Triggering TIM2 with Update of TIM1
760
Figure 222. Triggering TIM2 with Enable of TIM1
761
Table 171. TIM2 Internal Trigger Connection
769
Table 172. Output Control Bit for Standard Ocx Channels
780
Table 173. TIM2 Register Map and Reset Values
787
Figure 223. TIM16/TIM17 Block Diagram
791
Figure 224. Counter Timing Diagram with Prescaler Division Change from 1 to 2
793
Figure 225. Counter Timing Diagram with Prescaler Division Change from 1 to 4
793
Figure 226. Counter Timing Diagram, Internal Clock Divided by 1
795
Figure 227. Counter Timing Diagram, Internal Clock Divided by 2
795
Figure 228. Counter Timing Diagram, Internal Clock Divided by 4
796
Figure 229. Counter Timing Diagram, Internal Clock Divided by N
796
Preloaded)
797
Figure 232. Update Rate Examples Depending on Mode and Timx_Rcr Register Settings
799
Figure 233. Control Circuit in Normal Mode, Internal Clock Divided by 1
800
Figure 234. TI2 External Clock Connection Example
800
Figure 235. Control Circuit in External Clock Mode 1
801
Figure 236. Capture/Compare Channel (Example: Channel 1 Input Stage)
802
Figure 237. Capture/Compare Channel 1 Main Circuit
802
Figure 238. Output Stage of Capture/Compare Channel (Channel 1)
803
Figure 239. Output Compare Mode, Toggle on OC1
806
Figure 240. Edge-Aligned PWM Waveforms (ARR=8)
807
Figure 241. Complementary Output with Dead-Time Insertion
808
Figure 242. Dead-Time Waveforms with Delay Greater than the Negative Pulse
808
Figure 243. Dead-Time Waveforms with Delay Greater than the Positive Pulse
809
Figure 244. Output Behavior in Response to a Break
811
Table 174. Break Protection Disarming Conditions
812
Figure 245. Output Redirection
813
Figure 246. 6-Step Generation, COM Example (OSSR=1)
814
Figure 247. Example of One Pulse Mode
816
(Tim16/17)
829
Table 175. Output Control Bits for Complementary Ocx and Ocxn Channels with Break Feature
829
Table 176. TIM16/TIM17 Register Map and Reset Values
840
Figure 248. Low-Power Timer Block Diagram
843
Table 177. Stm32Wlex LPTIM Features
843
Table 178. LPTIM Input/Output Pins
844
Table 179. LPTIM Internal Signals
844
Table 180. LPTIM1 External Trigger Connection
844
Table 181. LPTIM2 External Trigger Connection
845
Table 182. LPTIM3 External Trigger Connection
845
Table 183. LPTIM1 Input 1 Connection
845
Table 184. LPTIM1 Input 2 Connection
845
Table 185. LPTIM2 Input 1 Connection
846
Table 186. LPTIM3 Input 1 Connection
846
Figure 249. Glitch Filter Timing Diagram
847
Table 187. Prescaler Division Ratios
847
And Set-Once Mode Activated (WAVE Bit Is Set)
849
Figure 250. LPTIM Output Waveform, Single Counting Mode Configuration When Repetition Register Content Is Different than Zero (with PRELOAD = 1)
849
Figure 252. LPTIM Output Waveform, Continuous Counting Mode Configuration
850
Figure 253. Waveform Generation
851
Table 188. Encoder Counting Scenarios
854
Figure 254. Encoder Mode Counting Sequence
855
Different from Zero (with PRELOAD = 1)
856
Table 189. Effect of Low-Power Modes on the LPTIM
857
Table 190. Interrupt Events
857
Table 191. LPTIM Register Map and Reset Values
869
Figure 256. IRTIM Internal Hardware Connections with TIM16 and TIM17
871
Figure 257. Independent Watchdog Block Diagram
872
Table 192. IWDG Register Map and Reset Values
880
Figure 258. Watchdog Block Diagram
882
Table 193. WWDG Internal Input/Output Signals
882
Figure 259. Window Watchdog Timing Diagram
883
Table 194. WWDG Register Map and Reset Values
886
Table 195. RTC Input/Output Pins
889
Table 196. RTC Internal Input/Output Signals
889
Table 197. RTC Interconnection
890
Table 198. PC13 Configuration
890
Table 199. RTC_OUT Mapping
892
Table 200. Effect of Low-Power Modes on RTC
905
Table 201. RTC Pins Functionality over Modes
905
Table 202. Interrupt Requests
906
Table 203. RTC Register Map and Reset Values
928
Figure 261. TAMP Block Diagram
931
Table 204. TAMP Input/Output Pins
932
Table 205. TAMP Internal Input/Output Signals
932
Table 206. TAMP Interconnection
932
Table 207. Effect of Low-Power Modes on TAMP
935
Table 208. Interrupt Requests
935
Table 209. TAMP Register Map and Reset Values
946
Table 210. Stm32Wlex I2C Implementation
948
Figure 262. I2C Block Diagram
949
Table 211. I2C Input/Output Pins
950
Table 212. I2C Internal Input/Output Signals
950
Figure 263. I2C Bus Protocol
951
Table 213. Comparison of Analog Vs. Digital Filters
952
Figure 264. Setup and Hold Timings
953
Table 214. I2C-Smbus Specification Data Setup and Hold Times
955
Figure 265. I2C Initialization Flow
956
Figure 266. Data Reception
957
Figure 267. Data Transmission
958
Table 215. I2C Configuration
959
Figure 268. Slave Initialization Flow
961
Figure 269. Transfer Sequence Flow for I2C Slave Transmitter, NOSTRETCH = 0
963
Figure 270. Transfer Sequence Flow for I2C Slave Transmitter, NOSTRETCH = 1
964
Figure 271. Transfer Bus Diagrams for I2C Slave Transmitter
965
Figure 272. Transfer Sequence Flow for Slave Receiver with NOSTRETCH = 0
966
Figure 273. Transfer Sequence Flow for Slave Receiver with NOSTRETCH = 1
967
Figure 274. Transfer Bus Diagrams for I2C Slave Receiver
967
Figure 275. Master Clock Generation
969
Table 216. I2C-Smbus Specification Clock Timings
970
Figure 276. Master Initialization Flow
971
Figure 277. 10-Bit Address Read Access with HEAD10R = 0
971
Figure 278. 10-Bit Address Read Access with HEAD10R = 1
972
Figure 279. Transfer Sequence Flow for I2C Master Transmitter for N≤255 Bytes
973
Figure 280. Transfer Sequence Flow for I2C Master Transmitter for N>255 Bytes
974
Figure 281. Transfer Bus Diagrams for I2C Master Transmitter
975
Figure 282. Transfer Sequence Flow for I2C Master Receiver for N≤255 Bytes
977
Figure 283. Transfer Sequence Flow for I2C Master Receiver for N >255 Bytes
978
Figure 284. Transfer Bus Diagrams for I2C Master Receiver
979
Table 217. Examples of Timing Settings for Fi2Cclk = 8 Mhz
980
Table 218. Examples of Timings Settings for Fi2Cclk = 16 Mhz
980
Figure 285. Timeout Intervals for T LOW:SEXT , T LOW:MEXT
983
Table 219. Smbus Timeout Specifications
983
Table 220. Smbus with PEC Configuration
985
(Max T IDLE = 50 Μs)
986
(Max T TIMEOUT = 25 Ms)
986
Table 221. Examples of TIMEOUTA Settings for Various I2CCLK Frequencies
986
Table 222. Examples of TIMEOUTB Settings for Various I2CCLK Frequencies
986
Figure 286. Transfer Sequence Flow for Smbus Slave Transmitter N Bytes + PEC
987
Figure 287. Transfer Bus Diagrams for Smbus Slave Transmitter (SBC=1)
987
Figure 288. Transfer Sequence Flow for Smbus Slave Receiver N Bytes + PEC
989
Figure 289. Bus Transfer Diagrams for Smbus Slave Receiver (SBC=1)
990
Figure 290. Bus Transfer Diagrams for Smbus Master Transmitter
991
Figure 291. Bus Transfer Diagrams for Smbus Master Receiver
993
Table 224. Effect of Low-Power Modes on the I2C
997
Table 225. I2C Interrupt Requests
998
Table 226. I2C Register Map and Reset Values
1013
Table 227. USART / LPUART Features
1017
Figure 292. USART Block Diagram
1018
Figure 293. Word Length Programming
1021
Figure 294. Configurable Stop Bits
1023
Figure 296. Start Bit Detection When Oversampling by 16 or 8
1027
Figure 297. Usart_Ker_Ck Clock Divider Block Diagram
1030
Figure 298. Data Sampling When Oversampling by 16
1031
Figure 299. Data Sampling When Oversampling by 8
1032
Table 228. Noise Detection from Sampled Data
1032
Table 229. Tolerance of the USART Receiver When BRR [3:0] = 0000
1035
Table 230. Tolerance of the USART Receiver When BRR[3:0] Is Different from 0000
1036
Figure 300. Mute Mode Using Idle Line Detection
1039
Figure 301. Mute Mode Using Address Mark Detection
1040
Table 231. USART Frame Formats
1041
Figure 302. Break Detection in LIN Mode (11-Bit Break Length - LBDL Bit Is Set)
1043
Figure 303. Break Detection in LIN Mode Vs. Framing Error Detection
1044
(M Bits = 00)
1045
Figure 304. USART Example of Synchronous Master Transmission
1045
Figure 305. USART Data Clock Timing Diagram in Synchronous Master Mode
1045
(M Bits = 01)
1046
(M Bits = 00)
1047
Figure 307. USART Data Clock Timing Diagram in Synchronous Slave Mode
1047
Figure 308. ISO 7816-3 Asynchronous Protocol
1049
Figure 309. Parity Error Detection Using the 1.5 Stop Bits
1051
Figure 310. Irda SIR ENDEC Block Diagram
1055
Figure 311. Irda Data Modulation (3/16) - Normal Mode
1055
Figure 312. Transmission Using DMA
1057
Figure 313. Reception Using DMA
1058
Figure 314. Hardware Flow Control between 2 Usarts
1058
Figure 315. RS232 RTS Flow Control
1059
Figure 316. RS232 CTS Flow Control
1060
FIFO Disabled)
1063
Figure 317. Wakeup Event Verified (Wakeup Event = Address Match, FIFO Disabled)
1063
Figure 318. Wakeup Event Not Verified
1063
Table 232. Effect of Low-Power Modes on the USART
1064
Table 233. USART Interrupt Requests
1065
Table 234. USART Register Map and Reset Values
1100
Table 235. USART / LPUART Features
1104
Figure 319. LPUART Block Diagram
1105
Figure 320. LPUART Word Length Programming
1107
Figure 321. Configurable Stop Bits
1109
Figure 323. Lpuart_Ker_Ck Clock Divider Block Diagram
1114
Table 236. Error Calculation for Programmed Baud Rates at Lpuart_Ker_Ck_Pres = 32.768 Khz
1115
Table 237. Error Calculation for Programmed Baud Rates at Fck = 100 Mhz
1116
Table 238. Tolerance of the LPUART Receiver
1117
Figure 324. Mute Mode Using Idle Line Detection
1118
Figure 325. Mute Mode Using Address Mark Detection
1119
Figure 326. Transmission Using DMA
1121
Figure 327. Reception Using DMA
1122
Figure 328. Hardware Flow Control between 2 Lpuarts
1123
Figure 329. RS232 RTS Flow Control
1123
Figure 330. RS232 CTS Flow Control
1124
FIFO Disabled)
1127
Figure 331. Wakeup Event Verified
1127
Figure 332. Wakeup Event Not Verified
1127
Table 240. Effect of Low-Power Modes on the LPUART
1128
Table 241. LPUART Interrupt Requests
1129
Table 242. LPUART Register Map and Reset Values
1153
Table 243. Stm32Wlex SPI and SPI/I2S Implementation
1156
Figure 333. SPI Block Diagram
1157
Figure 334. Full-Duplex Single Master/ Single Slave Application
1158
Figure 335. Half-Duplex Single Master/ Single Slave Application
1159
Figure 336. Simplex Single Master/Single Slave Application
1160
Slave in Receive-Only Mode)
1160
Figure 337. Master and Three Independent Slaves
1161
Figure 338. Multi-Master Application
1162
Figure 339. Hardware/Software Slave Select Management
1163
Figure 340. Data Clock Timing Diagram
1164
Figure 341. Data Alignment When Data Length Is Not Equal to 8-Bit or 16-Bit
1165
Figure 342. Packing Data in FIFO for Transmission and Reception
1169
Figure 343. Master Full-Duplex Communication
1172
Figure 344. Slave Full-Duplex Communication
1173
Figure 345. Master Full-Duplex Communication with CRC
1174
Figure 346. Master Full-Duplex Communication in Packed Mode
1175
Figure 347. NSSP Pulse Generation in Motorola SPI Master Mode
1178
Figure 348. TI Mode Transfer
1179
Table 244. SPI Interrupt Requests
1181
Figure 349. I2S Block Diagram
1182
Figure 350. I 2 S Philips Protocol Waveforms (16/32-Bit Full Accuracy)
1184
Figure 351. I 2 S Philips Standard Waveforms (24-Bit Frame)
1184
Figure 352. Transmitting 0X8Eaa33
1185
Figure 353. Receiving 0X8Eaa33
1185
Figure 354. I
1185
Figure 355. Example of 16-Bit Data Frame Extended to 32-Bit Channel Frame
1185
Figure 356. MSB Justified 16-Bit or 32-Bit Full-Accuracy Length
1186
Figure 357. MSB Justified 24-Bit Frame Length
1186
Figure 358. MSB Justified 16-Bit Extended to 32-Bit Packet Frame
1187
Figure 359. LSB Justified 16-Bit or 32-Bit Full-Accuracy
1187
Figure 360. LSB Justified 24-Bit Frame Length
1187
Figure 361. Operations Required to Transmit 0X3478Ae
1188
Figure 362. Operations Required to Receive 0X3478Ae
1188
Figure 363. LSB Justified 16-Bit Extended to 32-Bit Packet Frame
1188
Figure 364. Example of 16-Bit Data Frame Extended to 32-Bit Channel Frame
1189
Figure 365. PCM Standard Waveforms (16-Bit)
1189
Figure 366. PCM Standard Waveforms (16-Bit Extended to 32-Bit Packet Frame)
1190
Figure 367. Start Sequence in Master Mode
1191
Figure 368. Audio Sampling Frequency Definition
1192
Figure 369. I S Clock Generator Architecture
1192
Table 245. Audio-Frequency Precision Using 48 Mhz Clock Derived from HSE
1194
Table 246. I2S Interrupt Requests
1200
Table 247. SPI/I2S Register Map and Reset Values
1212
Figure 370. Block Diagram of Debug Support Infrastructure
1214
Table 248. Jtag/Serial-Wire Debug Port Pins
1214
Table 249. Single-Wire Trace Port Pins
1214
Figure 371. JTAG TAP State Machine
1217
Table 250. JTAG-DP Data Registers
1218
Table 251. Packet Request
1219
Table 252. ACK Response
1220
Table 253. Data Transfer
1220
Table 254. Debug Port Registers
1221
Table 255. DP Register Map and Reset Values
1229
Figure 372. Debug and Access Port Connections
1230
Table 256. MEM-AP Registers
1231
Figure 373. Debugger Connection to Debug Components
1233
Table 257. AP Register Map and Reset Values
1237
Table 258. DWT Register Map and Reset Values
1249
Table 259. ROM Table
1251
Figure 374. CPU Coresight Topology
1252
Table 260. ROM Table Register Map and Reset Values
1257
Table 261. FPB Register Map and Reset Values
1264
Table 262. ITM Register Map and Reset Values
1273
Figure 375. TPIU Architecture
1274
Table 263. TPIU Register Map and Reset Values
1284
Table 264. DBGMCU Register Map and Reset Values
1290
Table 265. Document Revision History
1297
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