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Manuals and User Guides for STMicroelectronics STM32WL5 Series MCU. We have
1
STMicroelectronics STM32WL5 Series MCU manual available for free PDF download: Reference Manual
STMicroelectronics STM32WL5 Series Reference Manual (1450 pages)
Advanced Arm-based 32-bit MCUs with Sub-GHz Radio Solution
Brand:
STMicroelectronics
| Category:
Microcontrollers
| Size: 28 MB
Table of Contents
Table of Contents
2
List of Tables
45
Documentation Conventions
59
General Information
59
List of Abbreviations for Registers
59
Availability of Peripherals
60
Glossary
60
Memory and Bus Architecture
61
System Architecture
61
Figure 1. System Architecture
62
S0: CPU1 I-Bus
62
S1: CPU1 D-Bus
62
S2: CPU1 S-Bus
62
S3: CPU2 S-Bus
62
Boot Configuration
63
S4, S5: DMA-Bus
63
Table 1. Device Boot Mode
63
CPU2 Boot
65
Memory Protection
66
SRAM Erase
66
Table 2. SRAM Erase Conditions
66
Figure 2. Memory Protection Example
68
Table 3. Memory Security and Privilege Access
69
Introduction
71
Memory Organization
71
Figure 3. Memory Map
72
Memory Map and Register Boundary Addresses
72
Table 4. Memory Map and Peripheral Register Boundary Addresses
73
CPU1 Bit Banding
76
Global Security Controller (GTZC)
78
GTZC Introduction
78
GTZC Main Features
78
GTZC Security System Architecture
78
Figure 4. GTZC Security Architecture
79
GTZC Block Diagram
79
GTZC Functional Description
79
Figure 5. GTZC Block Diagram
80
GTZC Internal Signals
80
Illegal Access Definition
80
Table 5. GTZC Internal Signals
80
Table 6. Memory Access Error Generation
82
Security Controller (TZSC)
83
Table 7. Peripheral Access Error Generation
83
Figure 6. Memory Protection Control Water Mark
84
Power-On/Reset State
84
Security Illegal Access Controller (TZIC)
84
GTZC TZSC Control Register (GTZC_TZSC_CR)
85
GTZC TZSC Registers
85
Interrupts
85
Table 8. TZSC Privileged Mpcwmn Register Memory Allocation
85
GTZC TZSC Security Configuration Register (GTZC_TZSC_SECCFGR1)
86
GTZC TZSC Privileged Configuration Register (GTZC_TZSC_PRIVCFGR1)
87
GTZC TZSC Unprivileged Watermark 1 Register (GTZC_TZSC_MPCWM1_UPWMR)
88
GTZC TZSC Unprivileged Writable Watermark 1 Register (GTZC_TZSC_MPCWM1_UPWWMR)
89
GTZC TZSC Unprivileged Watermark 2 Register (GTZC_TZSC_MPCWM2_UPWMR)
90
GTZC TZSC Unprivileged Watermark 3 Register (GTZC_TZSC_MPCWM3_UPWMR)
91
GTZC TZSC Register Map
92
Table 9. GTZC TZSC Register Map and Reset Values
92
GTZC TZIC Interrupt Enable Register 1 (GTZC_TZIC_IER1)
93
GTZC TZIC Registers
93
GTZC TZIC Status Register 1 (GTZC_TZIC_MISR1)
94
GTZC TZIC Interrupt Status Clear Register 1 (GTZC_TZIC_ICR1)
96
GTZC TZIC Register Map
97
Table 10. TZIC Register Map and Reset Values
97
Embedded Flash Memory (FLASH)
98
FLASH Functional Description
98
FLASH Introduction
98
FLASH Main Features
98
Flash Memory Organization
98
Empty Check
99
Table 11. Flash Memory - Single Bank Organization
99
Error Code Correction (ECC)
100
Read Access Latency
100
Table 12. Number of Wait States According to Flash Clock (HCLK3) Frequency
101
Adaptive Real-Time Memory Accelerator (ART Accelerator)
102
Figure 7. Sequential 16 Bits Instructions Execution
103
Flash Program and Erase Operations
105
Flash Main Memory Erase Sequences
106
Table 13. Page Erase Overview
106
Table 14. Mass Erase Overview
107
Flash Main Memory Programming Sequences
108
Table 15. Errors in Page-Based Row Programming
112
FLASH Option Bytes
113
Option Bytes Description
113
Table 16. Option Bytes Organization
113
Option Bytes Programming
114
Table 17. Option Loading Control
116
Introduction
117
RSSLIB Functions
117
Secure System Memory
117
Sub-Ghz Radio SPI Security
117
Flash Memory Protection
118
Readout Protection (RDP)
118
Table 18. Flash Memory Readout Protection Status
118
Table 19. RDP Regression from Level 1 to Level 0 and Memory Erase
120
Figure 8. Changing the RDP Level
121
Table 20. Access Status Versus Protection Level and Execution Modes
121
Proprietary Code Readout Protection (PCROP)
122
Write Protection (WRP)
123
CPU2 Security (ESE)
124
CPU1 Boot Lock Chain of Trust
126
CPU2 Boot Lock Chain of Trust
126
FLASH Program Erase Suspension
126
Hide Protection Area (HDPAD)
126
FLASH Interrupts
127
Illegal Access Interrupts
127
Table 23. Flash Interrupt Requests
127
Register Access Protection
128
FLASH Access Control Register (FLASH_ACR)
129
FLASH Registers
129
FLASH Access Control Register 2 (FLASH_ACR2)
130
FLASH Key Register (FLASH_KEYR)
131
FLASH Option Key Register (FLASH_OPTKEYR)
131
FLASH Status Register (FLASH_SR)
132
FLASH Control Register (FLASH_CR)
134
FLASH ECC Register (FLASH_ECCR)
136
FLASH Option Register (FLASH_OPTR)
137
(Flash_Pcrop1Aer)
140
FLASH PCROP Zone a End Address Register
140
FLASH PCROP Zone a Start Address Register (FLASH_PCROP1ASR)
140
FLASH WRP Area a Address Register (FLASH_WRP1AR)
141
FLASH WRP Area B Address Register (FLASH_WRP1BR)
142
(Flash_Pcrop1Ber)
143
(Flash_Pcrop1Bsr)
143
FLASH PCROP Zone B End Address Register
143
FLASH PCROP Zone B Start Address Register
143
(Flash_Ipccbr)
144
FLASH IPCC Mailbox Data Buffer Address Register
144
FLASH CPU2 Access Control Register (FLASH_C2ACR)
145
FLASH CPU2 Status Register (FLASH_C2SR)
145
FLASH CPU2 Control Register (FLASH_C2CR)
147
FLASH Secure Flash Start Address Register (FLASH_SFR)
149
(Flash_Srrvr)
150
FLASH Secure SRAM Start Address and CPU2 Reset Vector Register
150
FLASH Register Map
153
Table 25. Flash Interface Register Map and Reset Values
153
Sub-Ghz Radio (SUBGHZ)
155
Sub-Ghz Radio Introduction
155
Sub-Ghz Radio Main Features
155
Figure 9. Sub-Ghz Radio System Block Diagram
156
General Description
156
Sub-Ghz Radio Functional Description
156
Sub-Ghz Radio Signals
156
Table 26. Sub-Ghz Internal Input/Output Signals
156
Figure 10. High Output Power PA
157
Transmitter
157
Figure 11. Low Output Power PA
158
Receiver
158
Table 27. Sub-Ghz Radio Transmit High Output Power
158
Intermediate Frequencies
159
Rf-Pll
159
Table 28. FSK Mode Intermediate Frequencies
159
HSE32 Reference Clock
160
Internal Oscillators
160
Sub-Ghz Radio Clocks
160
Table 29. Lora Mode Intermediate Frequencies
160
Lora Modem
161
Sub-Ghz Radio Modems
161
Table 30. Spreading Factor, Chips/Symbol and Lora SNR
162
Table 31. Lora Bandwidth Setting
162
Lora Framing
163
Table 32. Coding Rate and Overhead Ratio
163
Figure 12. Lora Packet Frames Format
164
FSK Modem
165
Generic Framing
166
MSK Modem
166
Figure 13. Generic Packet Frames Format
167
BPSK Modem
168
BPSK Framing
169
Figure 14. Sub-Ghz RAM Data Buffer Operation
169
Sub-Ghz Radio Data Buffer
169
Receive Data Buffer Operation
170
Sub-Ghz Radio Operating Modes
170
Transmit Data Buffer Operation
170
Figure 15. Sub-Ghz Radio Operating Modes
171
Calibration Mode
172
Sleep Mode
172
Startup Mode
172
Frequency Synthesis Mode (FS)
173
Standby Mode
173
Transmit Mode (TX)
173
Active Mode Switching Time
174
Receive Mode (RX)
174
Figure 16. Sub-Ghz Radio BUSY Timing
175
Sub-Ghz Radio SPI Interface
175
Table 33. Operation Mode Transition BUSY Switching Time
175
Register and Buffer Access Commands
176
Sub-Ghz Radio Command Structure
176
Table 34. Command Structure
176
Operating Mode Commands
178
Figure 17. Receiver Listening Mode Timing
181
Sub-Ghz Radio Configuration Commands
183
Table 35. PA Optimal Setting and Operating Modes
185
Table 36. Recommended CAD Configuration Settings
187
Communication Status Information Commands
194
IRQ Interrupt Commands
197
Table 37. IRQ Bit Mapping and Definition
197
Miscellaneous Commands
199
Table 38. Image Calibration for ISM Bands
200
Set_Tcxomode Command
202
Table 39. Command Format Set_Tcxomode()
202
Sub-Ghz Radio Commands Overview
203
Table 40. Regtcxotrim and Timeout Bytes Definition
203
Table 41. Sub-Ghz Radio SPI Commands Overview
203
Basic Sequence for Lora, (G)MSK and (G)FSK Transmit Operation
205
Sub-Ghz Radio Application Configuration
205
Basic Sequence for Lora and (G)FSK Receive Operation
206
Basic Sequence for BPSK Transmit Operation
207
Sub-Ghz Radio Ramp-Up MSB Register (SUBGHZ_RAM_RAMPUPH)
207
Sub-Ghz Radio Registers
207
Sub-Ghz Radio Frame Limit MSB Register
208
Sub-Ghz Radio Ramp-Down LSB Register
208
Sub-Ghz Radio Ramp-Down MSB Register
208
Sub-Ghz Radio Ramp-Up LSB Register (SUBGHZ_RAM_RAMPUPL)
208
Sub-Ghz Radio Frame Limit LSB Register (SUBGHZ_RAM_FRAMELIML)
209
Sub-Ghz Radio Generic Bit Synchronization Register (SUBGHZ_GBSYNCR)
209
Sub-Ghz Radio Generic CFO MSB Register (SUBGHZ_GCFORH)
209
(Subghz_Gpktctl1Ar)
210
(Subghz_Gpktctl1R)
210
Sub-Ghz Radio Generic CFO LSB Register (SUBGHZ_GCFORL)
210
Sub-Ghz Radio Generic Packet Control 1 Register
210
Sub-Ghz Radio Generic Packet Control 1A Register
210
(Subghz_Grtxpldlen)
211
(Subghz_Gwhiteinirl)
211
Sub-Ghz Radio Generic Payload Length Register
211
Sub-Ghz Radio Generic Whitening LSB Register
211
Sub-Ghz Radio Random Number Register 1 (SUBGHZ_RNGR1)
218
Sub-Ghz Radio Random Number Register 2 (SUBGHZ_RNGR2)
218
Sub-Ghz Radio Random Number Register 3 (SUBGHZ_RNGR3)
218
(Subghz_Agcrssictl0R)
219
Sub-Ghz Radio AGC RSSI Control Register
219
Sub-Ghz Radio Random Number Register 0 (SUBGHZ_RNGR0)
219
Sub-Ghz Radio Receiver Gain Control Register (SUBGHZ_RXGAINCR)
219
Sub-Ghz Radio SD Resolution Register (SUBGHZ_SDCFG0R)
219
(Subghz_Agcgforstcfgr)
220
(Subghz_Agcgforstpowthr)
220
Sub-Ghz Radio AGC Reset Configuration Register
220
Sub-Ghz Radio AGC Reset Power Threshold Register
220
Sub-Ghz Radio Tx Clamp Register (SUBGHZ_TXCLAMPR)
220
(Subghz_Paocpr)
221
Sub-Ghz Radio Disable LNA Register (REG_ANA_LNA)
221
Sub-Ghz Radio Disable Mixer Register (REG_ANA_MIXER)
221
Sub-Ghz Radio PA over Current Protection Register
221
Sub-Ghz Radio RTC Control Register (SUBGHZ_RTCCTLR)
221
(Subghz_Rtcprdr1)
222
Sub-Ghz Radio RTC Period LSB Register (SUBGHZ_RTCPRDR0)
222
Sub-Ghz Radio RTC Period MID-Byte Register
222
Sub-Ghz Radio RTC Period MSB Register (SUBGHZ_RTCPRDR2)
222
(Subghz_Hseintrimr)
223
(Subghz_Hseouttrimr)
223
Sub-Ghz Radio HSE32 OSC_IN Capacitor Trim Register
223
Sub-Ghz Radio HSE32 OSC_OUT Capacitor Trim Register
223
Sub-Ghz Radio Power Control Register (SUBGHZ_PCR)
224
Sub-Ghz Radio SMPS Control 0 Register (SUBGHZ_SMPSC0R)
224
(Subghz_Regdrvcr)
225
Sub-Ghz Radio Regulator Drive Control Register
225
Sub-Ghz Radio SMPS Control 2 Register (SUBGHZ_SMPSC2R)
225
Sub-Ghz Radio Register Map
226
Table 42. SUBGHZ Register Map and Reset Values
226
Power Control (PWR)
228
Power Supplies
228
Figure 18. Power Supply Overview
229
Figure 19. Supply Configurations
230
Battery Backup Domain
231
Independent Analog Peripherals Supply
231
Dynamic Voltage Scaling Management
233
Voltage Regulator
233
Brownout Reset (BOR)
234
Power Supply Supervisor
234
Power-On Reset (Por)/Power-Down Reset (PDR)
234
Figure 20. Brownout Reset Waveform
235
Programmable Voltage Detector (PVD)
235
Figure 21. PVD Thresholds
236
Peripheral Voltage Monitoring (PVM)
236
Table 43. PVM Features
236
Figure 22. EOL Thresholds
237
Radio Busy Management
237
Radio End of Life (EOL)
237
Figure 23. Radio Busy Management
238
CPU2 Boot
239
Figure 24. CPU2 Boot Options
240
Low-Power Modes
241
Figure 25. Cpus Low-Power Modes Possible Transitions
244
Table 44. Low-Power Mode Summary
245
Table 45. Functionalities Depending on System Operating Mode
246
Table 46. MCU and Sub-Ghz Radio Operating Modes
248
Low-Power Run Mode (Lprun)
249
Run Mode
249
Enter Low-Power Mode
250
Exit Low-Power Mode
250
Table 47. Lprun
250
Sleep Mode
252
Table 48. CPU Wake-Up Versus System Operating Mode
252
Low-Power Sleep Mode (Lpsleep)
253
Table 49. Sleep Mode
253
Stop 0 Mode
254
Table 50. Lpsleep
254
Stop 1 Mode
256
Table 51. Stop 0 Mode
256
Stop 2 Mode
257
Table 52. Stop 1 Mode
257
Standby Mode
259
Table 53. Stop 2 Mode
259
Shutdown Mode
261
Table 54. Standby Mode
261
Auto-Wake-Up from Low-Power Mode
262
Table 55. Shutdown Mode
262
PWR Control Register 1 (PWR_CR1)
263
PWR Registers
263
PWR Control Register 2 (PWR_CR2)
265
PWR Control Register 3 (PWR_CR3)
266
PWR Control Register 4 (PWR_CR4)
268
PWR Status Register 1 (PWR_SR1)
269
Power Status Register 2 (PWR_SR2)
270
PWR Status Clear Register (PWR_SCR)
272
PWR Control Register 5 (PWR_CR5)
273
PWR Port a Pull-Down Control Register (PWR_PDCRA)
274
PWR Port a Pull-Up Control Register (PWR_PUCRA)
274
PWR Port B Pull-Down Control Register (PWR_PDCRB)
275
PWR Port B Pull-Up Control Register (PWR_PUCRB)
275
PWR Port C Pull-Down Control Register (PWR_PDCRC)
276
PWR Port C Pull-Up Control Register (PWR_PUCRC)
276
PWR Port H Pull-Down Control Register (PWR_PDCRH)
277
PWR Port H Pull-Up Control Register (PWR_PUCRH)
277
PWR CPU2 Control Register 1 (PWR_C2CR1)
278
PWR CPU2 Control Register 3 (PWR_C2CR3)
279
PWR Extended Status and Status Clear Register (PWR_EXTSCR)
280
PWR Security Configuration Register (PWR_SECCFGR)
282
PWR Sub-Ghz SPI Control Register (PWR_SUBGHZSPICR)
282
PWR Register Map
283
PWR RSS Command Register (PWR_RSSCMDR)
283
Table 56. PWR Register Map and Reset Values
283
Power Reset
286
Reset
286
Reset and Clock Control (RCC)
286
System Reset
286
Figure 26. Simplified Diagram of the Reset Circuit
287
Backup Domain Reset
288
Clocks
288
PKA SRAM Reset
288
Sub-Ghz Radio Reset
288
Figure 27. Clock Tree
291
HSE32 Clock with Trimming
291
Figure 28. HSE32 Clock Sources
292
Figure 29. HSE32 TCXO Control
293
HSI16 Clock
294
MSI Clock
294
Pll
295
Figure 30. LSE Clock Sources
296
LSE Clock
296
Clock Source Stabilization Time
297
LSI Clock
297
System Clock (SYSCLK) Selection
297
Table 57. Clock Source Stabilization Times
297
Clock Security System on HSE32 (CSS)
298
Clock Source Frequency Versus Voltage Scaling
298
Table 58. Clock Source Frequency
298
Clock Security System on LSE (LSECSS)
299
SPI2S2 Clock
299
Sub-Ghz Radio SPI Clock
299
Table 59. SPI2S2 I2S Clock PLL Configurations
299
ADC Clock
300
RTC Clock
300
Table 60. Sub-Ghz Radio SPI Clock Configurations
300
Timer Clock
300
Clock-Out Capability
301
True RNG Clock
301
Watchdog Clock
301
Figure 31. Frequency Measurement with TIM16 in Capture Mode
302
Figure 32. Frequency Measurement with TIM17 in Capture Mode
302
Internal/External Clock Measurement with TIM16/TIM17
302
Table 61. Peripheral Clock Enable
304
Table 62. Low-Power Debug Configurations
305
Table 63. RCC Register Map and Reset Values
366
Figure 33. HSEM Block Diagram
373
Table 64. HSEM Internal Input/Output Signals
373
Figure 34. Procedure State Diagram
374
Figure 35. Interrupt State Diagram
377
Table 65. Authorized AHB Bus Master Ids
378
Table 66. HSEM Register Map and Reset Values
384
Figure 36. IPCC Block Diagram
387
Table 67. IPCC Interface Signals
387
Figure 37. IPCC Simplex Channel Mode Transfer Timing
388
Table 68. Bits Used for the Communication
388
Figure 38. IPCC Simplex - Send Procedure State Diagram
389
Figure 39. IPCC Simplex - Receive Procedure State Diagram
390
Figure 40. IPCC Half-Duplex Channel Mode Transfer Timing
391
Figure 41. IPCC Half-Duplex - Send Procedure State Diagram
391
Figure 42. IPCC Half-Duplex - Receive Procedure State Diagram
392
Table 69. IPCC Register Map and Reset Values
399
Figure 43. Basic Structure of a Standard I/O Port Bit
401
Figure 44. Basic Structure of a 5V-Tolerant I/O Port Bit
402
Table 70. Port Bit Configurations
402
Figure 45. Input Floating/Pull-Up/Pull-Down Configurations
406
Figure 46. Output Configuration
407
Figure 47. Alternate Function Configuration
407
Figure 48. High Impedance Analog Configuration
408
Table 71. GPIOA Register Map and Reset Values
428
Table 72. GPIOB Register Map and Reset Values
429
Table 73. GPIOC Register Map and Reset Values
430
Table 74. GPIOH Register Map and Reset Values
431
Table 75. SYSCFG Register Map and Reset Values
444
Table 76. Stm32Wl5X Peripherals Interconnect Matrix
446
Table 77. DMA1 and DMA2 Implementation
455
Figure 49. DMA Block Diagram
456
Table 78. DMA Internal Input/Output Signals
457
Table 79. Programmable Data Width and Endian Behavior (When PINC = MINC = 1)
464
Table 80. DMA Interrupt Requests
466
Table 81. DMA Register Map and Reset Values
477
Table 82. DMAMUX Instantiation
481
Table 83. DMAMUX1: Assignment of Multiplexer Inputs to Resources
482
Table 84. DMAMUX1: Assignment of Trigger Inputs to Resources
483
Table 85. DMAMUX1: Assignment of Synchronization Inputs to Resources
483
Figure 50. DMAMUX Block Diagram
484
Table 86. DMAMUX Signals
485
Figure 51. Synchronization Mode of the DMAMUX Request Line Multiplexer Channel
488
Figure 52. Event Generation of the DMA Request Line Multiplexer Channel
488
Table 87. DMAMUX Interrupts
490
Table 88. DMAMUX Register Map and Reset Values
497
Figure 53. Interrupt Block Diagram
500
Table 89. CPU1 Vector Table
500
Table 90. CPU2 Vector Table
503
Figure 54. EXTI Block Diagram
507
Table 91. EXTI Pin Overview
507
Table 92. EVG Pin Overview
507
Table 93. Wake-Up Interrupts
508
Figure 55. Configurable Event Trigger Logic CPU Wake-Up
511
Table 94. EXTI Event Input Configurations and Register Control
511
Figure 56. Direct Event Trigger Logic CPU Wake-Up
512
Table 95. Masking Functionality
512
Table 96. EXTI Register Map Sections
513
Table 97. EXTI Register Map and Reset Values
523
Figure 57. CRC Calculation Unit Block Diagram
526
Table 98. CRC Internal Input/Output Signals
526
Table 99. CRC Register Map and Reset Values
531
Figure 58. ADC Block Diagram
534
Table 100. ADC Input/Output Pins
534
Table 101. ADC Internal Input/Output Signals
535
Table 102. External Triggers
535
Figure 59. ADC Calibration
537
Figure 60. Calibration Factor Forcing
537
Figure 61. Enabling/Disabling the ADC
538
Figure 62. ADC Clock Scheme
539
Table 103. Latency between Trigger and Start of Conversion
540
Figure 63. ADC Connectivity
541
Figure 64. Analog to Digital Conversion Time
546
Figure 65. ADC Conversion Timings
546
Figure 66. Stopping an Ongoing Conversion
547
Table 104. Configuring the Trigger Polarity
547
Table 105. Tsar Timings Depending on Resolution
549
Figure 67. Single Conversions of a Sequence, Software Trigger
550
Figure 68. Continuous Conversion of a Sequence, Software Trigger
550
Figure 69. Single Conversions of a Sequence, Hardware Trigger
551
Figure 70. Continuous Conversions of a Sequence, Hardware Trigger
551
Figure 71. Data Alignment and Resolution (Oversampling Disabled: OVSE = 0)
552
Figure 72. Example of Overrun (OVR)
553
Figure 73. Wait Mode Conversion (Continuous Mode, Software Trigger)
556
Figure 74. Behavior with WAIT = 0, AUTOFF = 1
557
Figure 76. Analog Watchdog Guarded Area
558
Table 106. Analog Watchdog Comparison
558
Table 107. Analog Watchdog 1 Channel Selection
558
Figure 77. Adc_Awdx_Out Signal Generation
560
Figure 78. Adc_Awdx_Out Signal Generation (Awdx Flag Not Cleared by Software)
560
Figure 79. Adc_Awdx_Out Signal Generation (on a Single Channel)
561
Figure 80. Analog Watchdog Threshold Update
561
Figure 81. 20-Bit to 16-Bit Result Truncation
562
Figure 82. Numerical Example with 5-Bits Shift and Rounding
563
Table 108. Maximum Output Results Vs N and M. Grayed Values Indicates Truncation
563
Figure 83. Triggered Oversampling Mode (TOVS Bit = 1)
565
Figure 84. Temperature Sensor and VREFINT Channel Block Diagram
566
Figure 85. VBAT Channel Block Diagram
568
Table 109. ADC Interrupts
568
Table 110. ADC Register Map and Reset Values
589
Figure 86. DAC Block Diagram
593
Table 111. DAC Features
593
Table 112. DAC Input/Output Pins
594
Table 113. DAC Internal Input/Output Signals
594
Table 114. DAC Interconnection
594
Figure 87. Data Registers in Single DAC Channel Mode
595
Figure 88. Timing Diagram for Conversion with Trigger Disabled TEN = 0
596
Figure 89. DAC LFSR Register Calculation Algorithm
598
Figure 90. DAC Conversion (SW Trigger Enabled) with LFSR Wave Generation
598
Figure 91. DAC Triangle Wave Generation
599
Figure 92. DAC Conversion (SW Trigger Enabled) with Triangle Wave Generation
599
Table 115. Sample and Refresh Timings
601
Figure 93. DAC Sample and Hold Mode Phase Diagram
602
Table 116. Channel Output Modes Summary
602
Table 117. Effect of Low-Power Modes on DAC
605
Table 118. DAC Interrupts
606
Table 119. DAC Register Map and Reset Values
615
Table 120. VREF Buffer Modes
617
Table 121. VREFBUF Register Map and Reset Values
619
Figure 94. Comparator Block Diagram
621
Table 122. COMP1 Input Plus Assignment
621
Table 123. COMP1 Input Minus Assignment
622
Table 124. COMP2 Input Plus Assignment
622
Table 125. COMP2 Input Minus Assignment
622
Figure 95. Window Mode
624
Figure 96. Comparator Hysteresis
624
Figure 97. Comparator Output Blanking
625
Table 126. Comparator Behavior in the Low-Power Modes
626
Table 127. Interrupt Control Bits
626
Table 128. COMP Register Map and Reset Values
631
Figure 98. RNG Block Diagram
633
Table 129. RNG Internal Input/Output Signals
633
Figure 99. NIST SP800-90B Entropy Source Model
634
Figure 100. RNG Initialization Overview
637
Table 130. RNG Interrupt Requests
641
Table 131. RNG Configurations
642
Table 132. RNG Register Map and Reset Map
646
Figure 101. AES Block Diagram
648
Table 133. AES Internal Input/Output Signals
648
Figure 102. ECB Encryption and Decryption Principle
650
Figure 103. CBC Encryption and Decryption Principle
651
Figure 104. CTR Encryption and Decryption Principle
652
Figure 105. GCM Encryption and Authentication Principle
653
Figure 106. GMAC Authentication Principle
653
Figure 107. CCM Encryption and Authentication Principle
654
Figure 108. Example of Suspend Mode Management
658
Figure 109. ECB Encryption
659
Figure 110. ECB Decryption
659
Figure 111. CBC Encryption
660
Figure 112. CBC Decryption
660
Figure 113. ECB/CBC Encryption (Mode 1)
661
Figure 114. ECB/CBC Decryption (Mode 3)
662
Figure 115. Message Construction in CTR Mode
663
Figure 116. CTR Encryption
664
Figure 117. CTR Decryption
664
Table 134. CTR Mode Initialization Vector Definition
664
Figure 118. Message Construction in GCM
666
Table 135. GCM Last Block Definition
666
Figure 119. GCM Authenticated Encryption
667
Table 136. Initialization of Aes_Ivrx Registers in GCM Mode
667
Figure 120. Message Construction in GMAC Mode
671
Figure 121. GMAC Authentication Mode
671
Figure 122. Message Construction in CCM Mode
672
Figure 123. CCM Mode Authenticated Encryption
674
Table 137. Initialization of Aes_Ivrx Registers in CCM Mode
674
Figure 124. 128-Bit Block Construction with Respect to Data Swap
678
Table 138. Key Endianness in Aes_Keyrx Registers (128- or 256-Bit Key Length)
679
Figure 125. DMA Transfer of a 128-Bit Data Block During Input Phase
680
Figure 126. DMA Transfer of a 128-Bit Data Block During Output Phase
681
Table 139. AES Interrupt Requests
682
Table 140. Processing Latency for ECB, CBC and CTR
682
Table 141. Processing Latency for GCM and CCM (in Clock Cycles)
683
Table 142. AES Register Map and Reset Values
693
Figure 127. PKA Block Diagram
696
Table 143. Internal Input/Output Signals
696
Table 144. PKA Integer Arithmetic Functions List
697
Table 145. PKA Prime Field (Fp) Elliptic Curve Functions List
697
Table 146. Montgomery Parameter Computation
702
Table 147. Modular Addition
703
Table 148. Modular Subtraction
703
Table 149. Montgomery Multiplication
704
Table 150. Modular Exponentiation (Normal Mode)
705
Table 151. Modular Exponentiation (Fast Mode)
705
Table 152. Modular Inversion
705
Table 153. Modular Reduction
706
Table 154. Arithmetic Addition
706
Table 155. Arithmetic Subtraction
706
Table 156. Arithmetic Multiplication
707
Table 157. Arithmetic Comparison
707
Table 158. CRT Exponentiation
708
Table 159. Point on Elliptic Curve Fp Check
709
Table 160. ECC Fp Scalar Multiplication
709
Table 161. ECC Fp Scalar Multiplication (Fast Mode)
710
Table 162. ECDSA Sign - Inputs
711
Table 163. ECDSA Sign - Outputs
711
Table 164. Extended ECDSA Sign (Extra Outputs)
712
Table 165. ECDSA Verification (Inputs)
712
Table 166. ECDSA Verification (Outputs)
712
Table 167. Family of Supported Curves for ECC Operations
713
Table 168. Modular Exponentiation Computation Times
715
Table 169. ECC Scalar Multiplication Computation Times
715
Table 170. ECDSA Signature Average Computation Times
715
Table 171. ECDSA Verification Average Computation Times
716
Table 172. Point on Elliptic Curve Fp Check Average Computation Times
716
Table 173. Montgomery Parameters Average Computation Times
716
Table 174. PKA Interrupt Requests
716
Table 175. PKA Register Map and Reset Values
720
Figure 128. Advanced-Control Timer Block Diagram
723
Figure 129. Counter Timing Diagram with Prescaler Division Change from 1 to 2
725
Figure 130. Counter Timing Diagram with Prescaler Division Change from 1 to 4
725
Figure 131. Counter Timing Diagram, Internal Clock Divided by 1
727
Figure 132. Counter Timing Diagram, Internal Clock Divided by 2
727
Figure 133. Counter Timing Diagram, Internal Clock Divided by 4
728
Figure 134. Counter Timing Diagram, Internal Clock Divided by N
728
Figure 135. Counter Timing Diagram, Update Event When ARPE=0 (Timx_Arr Not Preloaded)
729
Figure 136. Counter Timing Diagram, Update Event When ARPE=1 (Timx_Arr Preloaded)
729
Figure 137. Counter Timing Diagram, Internal Clock Divided by 1
731
Figure 138. Counter Timing Diagram, Internal Clock Divided by 2
731
Figure 139. Counter Timing Diagram, Internal Clock Divided by 4
732
Figure 140. Counter Timing Diagram, Internal Clock Divided by N
732
Figure 141. Counter Timing Diagram, Update Event When Repetition Counter Is Not Used
733
Figure 142. Counter Timing Diagram, Internal Clock Divided by 1, Timx_Arr = 0X6
734
Figure 143. Counter Timing Diagram, Internal Clock Divided by 2
735
Figure 144. Counter Timing Diagram, Internal Clock Divided by 4, Timx_Arr=0X36
735
Figure 145. Counter Timing Diagram, Internal Clock Divided by N
736
Figure 146. Counter Timing Diagram, Update Event with ARPE=1 (Counter Underflow)
736
Figure 147. Counter Timing Diagram, Update Event with ARPE=1 (Counter Overflow)
737
Figure 148. Update Rate Examples Depending on Mode and Timx_Rcr Register Settings
738
Figure 149. External Trigger Input Block
739
Figure 151. Control Circuit in Normal Mode, Internal Clock Divided by 1
740
Figure 152. TI2 External Clock Connection Example
741
Figure 153. Control Circuit in External Clock Mode 1
742
Figure 154. External Trigger Input Block
742
Figure 155. Control Circuit in External Clock Mode 2
743
Figure 156. Capture/Compare Channel (Example: Channel 1 Input Stage)
744
Figure 157. Capture/Compare Channel 1 Main Circuit
744
Figure 158. Output Stage of Capture/Compare Channel (Channel 1, Idem Ch. 2 and 3)
745
Figure 159. Output Stage of Capture/Compare Channel (Channel 4)
745
Figure 160. Output Stage of Capture/Compare Channel (Channel 5, Idem Ch. 6)
746
Figure 161. PWM Input Mode Timing
748
Figure 162. Output Compare Mode, Toggle on OC1
750
Figure 163. Edge-Aligned PWM Waveforms (ARR=8)
751
Figure 164. Center-Aligned PWM Waveforms (ARR=8)
752
Figure 165. Generation of 2 Phase-Shifted PWM Signals with 50% Duty Cycle
754
Figure 166. Combined PWM Mode on Channel 1 and 3
755
Figure 167. 3-Phase Combined PWM Signals with Multiple Trigger Pulses Per Period
756
Figure 168. Complementary Output with Dead-Time Insertion
757
Figure 169. Dead-Time Waveforms with Delay Greater than the Negative Pulse
757
Figure 170. Dead-Time Waveforms with Delay Greater than the Positive Pulse
758
Figure 171. Break and Break2 Circuitry Overview
760
Figure 172. Various Output Behavior in Response to a Break Event on BRK (OSSI = 1)
762
Figure 173. PWM Output State Following BRK and BRK2 Pins Assertion (OSSI=1)
763
Table 176. Behavior of Timer Outputs Versus BRK/BRK2 Inputs
763
Figure 174. PWM Output State Following BRK Assertion (OSSI=0)
764
Figure 175. Output Redirection (BRK2 Request Not Represented)
765
Table 177. Break Protection Disarming Conditions
765
Figure 176. Clearing Timx Ocxref
766
Figure 177. 6-Step Generation, COM Example (OSSR=1)
767
Figure 178. Example of One Pulse Mode
768
Figure 179. Retriggerable One Pulse Mode
770
Figure 180. Example of Counter Operation in Encoder Interface Mode
771
Table 178. Counting Direction Versus Encoder Signals
771
Figure 181. Example of Encoder Interface Mode with TI1FP1 Polarity Inverted
772
Figure 182. Measuring Time Interval between Edges on 3 Signals
773
Figure 183. Example of Hall Sensor Interface
775
Figure 184. Control Circuit in Reset Mode
776
Figure 185. Control Circuit in Gated Mode
777
Figure 186. Control Circuit in Trigger Mode
778
Figure 187. Control Circuit in External Clock Mode 2 + Trigger Mode
779
Table 179. TIM1 Internal Trigger Connection
788
Table 180. Output Control Bits for Complementary Ocx and Ocxn Channels with Break Feature
802
Table 181. TIM1 Register Map and Reset Values
819
Figure 188. General-Purpose Timer Block Diagram
823
Figure 189. Counter Timing Diagram with Prescaler Division Change from 1 to 2
825
Figure 190. Counter Timing Diagram with Prescaler Division Change from 1 to 4
825
Figure 191. Counter Timing Diagram, Internal Clock Divided by 1
826
Figure 192. Counter Timing Diagram, Internal Clock Divided by 2
827
Figure 193. Counter Timing Diagram, Internal Clock Divided by 4
827
Figure 194. Counter Timing Diagram, Internal Clock Divided by N
828
Figure 195. Counter Timing Diagram, Update Event When ARPE=0 (Timx_Arr Not Preloaded)
828
Figure 196. Counter Timing Diagram, Update Event When ARPE=1 (Timx_Arr Preloaded)
829
Figure 197. Counter Timing Diagram, Internal Clock Divided by 1
830
Figure 198. Counter Timing Diagram, Internal Clock Divided by 2
830
Figure 199. Counter Timing Diagram, Internal Clock Divided by 4
831
Figure 200. Counter Timing Diagram, Internal Clock Divided by N
831
Figure 201. Counter Timing Diagram, Update Event
832
Figure 202. Counter Timing Diagram, Internal Clock Divided by 1, Timx_Arr=0X6
833
Figure 203. Counter Timing Diagram, Internal Clock Divided by 2
834
Figure 204. Counter Timing Diagram, Internal Clock Divided by 4, Timx_Arr=0X36
834
Figure 205. Counter Timing Diagram, Internal Clock Divided by N
835
Figure 206. Counter Timing Diagram, Update Event with ARPE=1 (Counter Underflow)
835
Figure 207. Counter Timing Diagram, Update Event with ARPE=1 (Counter Overflow)
836
Figure 208. Control Circuit in Normal Mode, Internal Clock Divided by 1
837
Figure 209. TI2 External Clock Connection Example
837
Figure 210. Control Circuit in External Clock Mode 1
838
Figure 211. External Trigger Input Block
839
Figure 212. Control Circuit in External Clock Mode 2
840
Figure 213. Capture/Compare Channel (Example: Channel 1 Input Stage)
840
Figure 214. Capture/Compare Channel 1 Main Circuit
841
Figure 215. Output Stage of Capture/Compare Channel (Channel 1)
841
Figure 216. PWM Input Mode Timing
843
Figure 217. Output Compare Mode, Toggle on OC1
845
Figure 218. Edge-Aligned PWM Waveforms (ARR=8)
846
Figure 219. Center-Aligned PWM Waveforms (ARR=8)
848
Figure 220. Generation of 2 Phase-Shifted PWM Signals with 50% Duty Cycle
849
Figure 221. Combined PWM Mode on Channels 1 and 3
850
Figure 222. Clearing Timx Ocxref
851
Figure 223. Example of One-Pulse Mode
852
Figure 224. Retriggerable One-Pulse Mode
854
Figure 225. Example of Counter Operation in Encoder Interface Mode
855
Table 182. Counting Direction Versus Encoder Signals
855
Figure 226. Example of Encoder Interface Mode with TI1FP1 Polarity Inverted
856
Figure 227. Control Circuit in Reset Mode
857
Figure 228. Control Circuit in Gated Mode
858
Figure 229. Control Circuit in Trigger Mode
859
Figure 230. Control Circuit in External Clock Mode 2 + Trigger Mode
860
Figure 231. Master/Slave Timer Example
860
Figure 232. Master/Slave Connection Example with 1 Channel Only Timers
861
Figure 233. Gating TIM2 with OC1REF of TIM1
862
Figure 234. Gating TIM2 with Enable of TIM1
863
Figure 235. Triggering TIM2 with Update of TIM1
863
Figure 236. Triggering TIM2 with Enable of TIM1
864
Table 183. TIM2 Internal Trigger Connection
872
Table 184. Output Control Bit for Standard Ocx Channels
883
Table 185. TIM2 Register Map and Reset Values
890
Figure 237. TIM16/TIM17 Block Diagram
894
Figure 238. Counter Timing Diagram with Prescaler Division Change from 1 to 2
896
Figure 239. Counter Timing Diagram with Prescaler Division Change from 1 to 4
896
Figure 240. Counter Timing Diagram, Internal Clock Divided by 1
898
Figure 241. Counter Timing Diagram, Internal Clock Divided by 2
898
Figure 242. Counter Timing Diagram, Internal Clock Divided by 4
899
Figure 243. Counter Timing Diagram, Internal Clock Divided by N
899
Preloaded)
900
Figure 246. Update Rate Examples Depending on Mode and Timx_Rcr Register Settings
902
Figure 247. Control Circuit in Normal Mode, Internal Clock Divided by 1
903
Figure 248. TI2 External Clock Connection Example
903
Figure 249. Control Circuit in External Clock Mode 1
904
Figure 250. Capture/Compare Channel (Example: Channel 1 Input Stage)
905
Figure 251. Capture/Compare Channel 1 Main Circuit
905
Figure 252. Output Stage of Capture/Compare Channel (Channel 1)
906
Figure 253. Output Compare Mode, Toggle on OC1
909
Figure 254. Edge-Aligned PWM Waveforms (ARR=8)
910
Figure 255. Complementary Output with Dead-Time Insertion
911
Figure 256. Dead-Time Waveforms with Delay Greater than the Negative Pulse
911
Figure 257. Dead-Time Waveforms with Delay Greater than the Positive Pulse
912
Figure 258. Output Behavior in Response to a Break
914
Table 186. Break Protection Disarming Conditions
915
Figure 259. Output Redirection
916
Figure 260. 6-Step Generation, COM Example (OSSR=1)
917
Figure 261. Example of One Pulse Mode
918
(Tim16/17)
932
Table 187. Output Control Bits for Complementary Ocx and Ocxn Channels with Break Feature
932
Table 188. TIM16/TIM17 Register Map and Reset Values
943
Table 189. Stm32Wl5X LPTIM Features
945
Figure 262. Low-Power Timer Block Diagram
946
Table 190. LPTIM Input/Output Pins
946
Table 191. LPTIM Internal Signals
947
Table 192. LPTIM1 External Trigger Connection
947
Table 193. LPTIM2 External Trigger Connection
947
Table 194. LPTIM3 External Trigger Connection
948
Table 195. LPTIM1 Input 1 Connection
948
Table 196. LPTIM1 Input 2 Connection
948
Table 197. LPTIM2 Input 1 Connection
948
Table 198. LPTIM3 Input 1 Connection
948
Figure 263. Glitch Filter Timing Diagram
950
Table 199. Prescaler Division Ratios
950
Figure 264. LPTIM Output Waveform, Single Counting Mode Configuration When Repetition Register Content Is Different than Zero (with PRELOAD = 1)
951
And Set-Once Mode Activated (WAVE Bit Is Set)
952
Figure 266. LPTIM Output Waveform, Continuous Counting Mode Configuration
952
Figure 267. Waveform Generation
954
Table 200. Encoder Counting Scenarios
957
Figure 268. Encoder Mode Counting Sequence
958
Different from Zero (with PRELOAD = 1)
959
Table 201. Effect of Low-Power Modes on the LPTIM
960
Table 202. Interrupt Events
960
Table 203. LPTIM Register Map and Reset Values
971
Figure 270. IRTIM Internal Hardware Connections with TIM16 and TIM17
973
Figure 271. Independent Watchdog Block Diagram
974
Table 204. IWDG Register Map and Reset Values
982
Figure 272. Watchdog Block Diagram
984
Table 205. WWDG Internal Input/Output Signals
984
Figure 273. Window Watchdog Timing Diagram
985
Table 206. WWDG Register Map and Reset Values
988
Table 207. RTC Input/Output Pins
991
Table 208. RTC Internal Input/Output Signals
991
Table 209. RTC Interconnection
992
Table 210. PC13 Configuration
992
Table 211. RTC_OUT Mapping
994
Table 212. Effect of Low-Power Modes on RTC
1007
Table 213. RTC Pins Functionality over Modes
1007
Table 214. Interrupt Requests
1008
Table 215. RTC Register Map and Reset Values
1030
Figure 275. TAMP Block Diagram
1033
Table 216. TAMP Input/Output Pins
1034
Table 217. TAMP Internal Input/Output Signals
1034
Table 218. TAMP Interconnection
1034
Table 219. Effect of Low-Power Modes on TAMP
1037
Table 220. Interrupt Requests
1037
Table 221. TAMP Register Map and Reset Values
1048
Table 222. Stm32Wl5X I2C Implementation
1050
Figure 276. I2C Block Diagram
1051
Table 223. I2C Input/Output Pins
1052
Table 224. I2C Internal Input/Output Signals
1052
Figure 277. I2C Bus Protocol
1053
Table 225. Comparison of Analog Vs. Digital Filters
1054
Figure 278. Setup and Hold Timings
1055
Table 226. I2C-Smbus Specification Data Setup and Hold Times
1056
Figure 279. I2C Initialization Flow
1057
Figure 280. Data Reception
1058
Figure 281. Data Transmission
1059
Table 227. I2C Configuration
1060
Figure 282. Slave Initialization Flow
1062
Figure 283. Transfer Sequence Flow for I2C Slave Transmitter, NOSTRETCH = 0
1064
Figure 284. Transfer Sequence Flow for I2C Slave Transmitter, NOSTRETCH = 1
1065
Figure 285. Transfer Bus Diagrams for I2C Slave Transmitter (Mandatory Events Only)
1066
Figure 286. Transfer Sequence Flow for Slave Receiver with NOSTRETCH = 0
1067
(Mandatory Events Only)
1068
Figure 287. Transfer Sequence Flow for Slave Receiver with NOSTRETCH = 1
1068
Figure 288. Transfer Bus Diagrams for I2C Slave Receiver
1068
Figure 289. Master Clock Generation
1070
Table 228. I2C-Smbus Specification Clock Timings
1071
Figure 290. Master Initialization Flow
1072
Figure 291. 10-Bit Address Read Access with HEAD10R = 0
1072
Figure 292. 10-Bit Address Read Access with HEAD10R = 1
1073
Figure 293. Transfer Sequence Flow for I2C Master Transmitter for N ≤ 255 Bytes
1074
Figure 294. Transfer Sequence Flow for I2C Master Transmitter for N > 255 Bytes
1075
(Mandatory Events Only)
1076
Figure 295. Transfer Bus Diagrams for I2C Master Transmitter
1076
Figure 296. Transfer Sequence Flow for I2C Master Receiver for N ≤ 255 Bytes
1078
Figure 297. Transfer Sequence Flow for I2C Master Receiver for N > 255 Bytes
1079
(Mandatory Events Only)
1080
Figure 298. Transfer Bus Diagrams for I2C Master Receiver
1080
Table 229. Examples of Timing Settings for Fi2Cclk = 8 Mhz
1081
Table 230. Examples of Timing Settings for Fi2Cclk = 16 Mhz
1081
Table 231. Smbus Timeout Specifications
1083
Figure 299. Timeout Intervals for T LOW:SEXT , T LOW:MEXT
1084
Table 232. Smbus with PEC Configuration
1085
IDLE = 50 Μs)
1086
Table 233. Examples of TIMEOUTA Settings (Max T TIMEOUT = 25 Ms)
1086
Table 234. Examples of TIMEOUTB Settings
1086
Figure 300. Transfer Sequence Flow for Smbus Slave Transmitter N Bytes + PEC
1087
Figure 301. Transfer Bus Diagrams for Smbus Slave Transmitter (SBC = 1)
1088
Figure 302. Transfer Sequence Flow for Smbus Slave Receiver N Bytes + PEC
1089
Figure 303. Bus Transfer Diagrams for Smbus Slave Receiver (SBC = 1)
1090
Figure 304. Bus Transfer Diagrams for Smbus Master Transmitter
1091
Figure 305. Bus Transfer Diagrams for Smbus Master Receiver
1093
Table 236. Effect of Low-Power Modes on the I2C
1097
Table 237. I2C Interrupt Requests
1098
Table 238. I2C Register Map and Reset Values
1112
Table 239. USART / LPUART Features
1116
Figure 306. USART Block Diagram
1117
Figure 307. Word Length Programming
1120
Figure 308. Configurable Stop Bits
1122
Figure 310. Start Bit Detection When Oversampling by 16 or 8
1126
Figure 311. Usart_Ker_Ck Clock Divider Block Diagram
1129
Figure 312. Data Sampling When Oversampling by 16
1130
Figure 313. Data Sampling When Oversampling by 8
1131
Table 240. Noise Detection from Sampled Data
1131
Table 241. Tolerance of the USART Receiver When BRR [3:0] = 0000
1134
Table 242. Tolerance of the USART Receiver When BRR[3:0] Is Different from 0000
1135
Figure 314. Mute Mode Using Idle Line Detection
1138
Figure 315. Mute Mode Using Address Mark Detection
1139
Table 243. USART Frame Formats
1140
Figure 316. Break Detection in LIN Mode (11-Bit Break Length - LBDL Bit Is Set)
1142
Figure 317. Break Detection in LIN Mode Vs. Framing Error Detection
1143
(M Bits = 00)
1144
Figure 318. USART Example of Synchronous Master Transmission
1144
Figure 319. USART Data Clock Timing Diagram in Synchronous Master Mode
1144
(M Bits = 01)
1145
(M Bits = 00)
1146
Figure 321. USART Data Clock Timing Diagram in Synchronous Slave Mode
1146
Figure 322. ISO 7816-3 Asynchronous Protocol
1148
Figure 323. Parity Error Detection Using the 1.5 Stop Bits
1150
Figure 324. Irda SIR ENDEC Block Diagram
1154
Figure 325. Irda Data Modulation (3/16) - Normal Mode
1154
Figure 326. Transmission Using DMA
1156
Figure 327. Reception Using DMA
1157
Figure 328. Hardware Flow Control between 2 Usarts
1157
Figure 329. RS232 RTS Flow Control
1158
Figure 330. RS232 CTS Flow Control
1159
FIFO Disabled)
1162
Figure 331. Wake-Up Event Verified (Wake-Up Event = Address Match, FIFO Disabled)
1162
Figure 332. Wake-Up Event Not Verified
1162
Table 244. Effect of Low-Power Modes on the USART
1163
Table 245. USART Interrupt Requests
1164
Table 246. USART Register Map and Reset Values
1199
Table 247. USART / LPUART Features
1203
Figure 333. LPUART Block Diagram
1204
Figure 334. LPUART Word Length Programming
1206
Figure 335. Configurable Stop Bits
1208
Figure 337. Lpuart_Ker_Ck Clock Divider Block Diagram
1213
Table 248. Error Calculation for Programmed Baud Rates at Lpuart_Ker_Ck_Pres = 32.768 Khz
1214
Table 249. Error Calculation for Programmed Baud Rates at Fck = 100 Mhz
1215
Table 250. Tolerance of the LPUART Receiver
1216
Figure 338. Mute Mode Using Idle Line Detection
1217
Figure 339. Mute Mode Using Address Mark Detection
1218
Figure 340. Transmission Using DMA
1220
Figure 341. Reception Using DMA
1221
Figure 342. Hardware Flow Control between 2 Lpuarts
1222
Figure 343. RS232 RTS Flow Control
1222
Figure 344. RS232 CTS Flow Control
1223
FIFO Disabled)
1226
Figure 345. Wake-Up Event Verified
1226
Figure 346. Wake-Up Event Not Verified
1226
Table 252. Effect of Low-Power Modes on the LPUART
1227
Table 253. LPUART Interrupt Requests
1228
Table 254. LPUART Register Map and Reset Values
1252
Table 255. Stm32Wl5X SPI and SPI/I2S Implementation
1255
Figure 347. SPI Block Diagram
1256
Figure 348. Full-Duplex Single Master/ Single Slave Application
1257
Figure 349. Half-Duplex Single Master/ Single Slave Application
1258
Figure 350. Simplex Single Master/Single Slave Application
1259
Slave in Receive-Only Mode)
1259
Figure 351. Master and Three Independent Slaves
1260
Figure 352. Multimaster Application
1261
Figure 353. Hardware/Software Slave Select Management
1262
Figure 354. Data Clock Timing Diagram
1263
Figure 355. Data Alignment When Data Length Is Not Equal to 8-Bit or 16-Bit
1264
Figure 356. Packing Data in FIFO for Transmission and Reception
1268
Figure 357. Master Full-Duplex Communication
1271
Figure 358. Slave Full-Duplex Communication
1272
Figure 359. Master Full-Duplex Communication with CRC
1273
Figure 360. Master Full-Duplex Communication in Packed Mode
1274
Figure 361. NSSP Pulse Generation in Motorola SPI Master Mode
1277
Figure 362. TI Mode Transfer
1278
Table 256. SPI Interrupt Requests
1280
Figure 363. I2S Block Diagram
1281
Figure 364. I 2 S Philips Protocol Waveforms (16/32-Bit Full Accuracy)
1283
Figure 365. I 2 S Philips Standard Waveforms (24-Bit Frame)
1283
Figure 366. Transmitting 0X8Eaa33
1284
Figure 367. Receiving 0X8Eaa33
1284
Figure 368. I
1284
Figure 369. Example of 16-Bit Data Frame Extended to 32-Bit Channel Frame
1284
Figure 370. MSB Justified 16-Bit or 32-Bit Full-Accuracy Length
1285
Figure 371. MSB Justified 24-Bit Frame Length
1285
Figure 372. MSB Justified 16-Bit Extended to 32-Bit Packet Frame
1286
Figure 373. LSB Justified 16-Bit or 32-Bit Full-Accuracy
1286
Figure 374. LSB Justified 24-Bit Frame Length
1286
Figure 375. Operations Required to Transmit 0X3478Ae
1287
Figure 376. Operations Required to Receive 0X3478Ae
1287
Figure 377. LSB Justified 16-Bit Extended to 32-Bit Packet Frame
1287
Figure 378. Example of 16-Bit Data Frame Extended to 32-Bit Channel Frame
1288
Figure 379. PCM Standard Waveforms (16-Bit)
1288
Figure 380. PCM Standard Waveforms (16-Bit Extended to 32-Bit Packet Frame)
1289
Figure 381. Start Sequence in Master Mode
1290
Figure 382. Audio Sampling Frequency Definition
1291
Figure 383. I S Clock Generator Architecture
1291
Table 257. Audio-Frequency Precision Using 48 Mhz Clock Derived from HSE
1293
Table 258. I2S Interrupt Requests
1299
Table 259. SPI/I2S Register Map and Reset Values
1311
Figure 384. Block Diagram of Debug Support Infrastructure
1313
Table 260. Jtag/Serial-Wire Debug Port Pins
1314
Table 261. Single-Wire Trace Port Pins
1314
Table 262. Debug Access Control Overview
1314
Figure 385. JTAG TAP State Machine
1317
Table 263. JTAG-DP Data Registers
1318
Table 264. Packet Request
1319
Table 265. ACK Response
1320
Table 266. Data Transfer
1320
Table 267. Debug Port Registers
1321
Table 268. DP Register Map and Reset Values
1329
Figure 386. Debug and Access Port Connections
1330
Table 269. MEM-AP Registers
1331
Figure 387. Debugger Connection to Debug Components
1333
Table 270. AP Register Map and Reset Values
1337
Table 271. DWT Register Map and Reset Values
1349
Figure 388. Embedded Cross Trigger
1351
Table 272. CPU2 CTI Inputs
1351
Table 273. CPU2 CTI Outputs
1352
Table 274. CPU1 CTI Inputs
1352
Table 275. CPU1 CTI Outputs
1352
Figure 389. Mapping Trigger Inputs to Outputs
1353
Figure 390. Cross Trigger Configuration Example
1354
Table 276. CTI Register Map and Reset Values
1368
Table 277. CPU1 ROM Table
1372
Figure 391. CPU1 Coresight Topology
1373
Table 278. CPU1 ROM Table Register Map and Reset Values
1378
Table 279. CPU1 FPB Register Map and Reset Values
1385
Table 280. CPU1 ITM Register Map and Reset Values
1394
Figure 392. TPIU Architecture
1395
Table 281. TPIU Register Map and Reset Values
1405
Table 282. DBGMCU Register Map and Reset Values
1413
Table 283. ROM1 Table
1415
Table 284. ROM2 Table
1415
Figure 393. CPU2 Coresight Topology
1416
Table 285. CPU2 Processor ROM Table Register Map and Reset Values
1421
Table 286. CPU2 ROM Table Register Map and Reset Values
1426
Table 287. CPU2 BPU Register Map and Reset Values
1434
Table 288. Document Revision History
1441
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