STMicroelectronics SPC572L series Reference Manual page 1368

SENT Receiver (SRX)
Field
Slow Serial Message DMA Underflow Interrupt Enable: Enables interrupt assertion when there is an
underflow condition on Slow Message DMA registers. Default value is 0.
23
SMDUIE
0 – Interrupt is disabled
1 – Interrupt is enabled
24 Reserved. Read returns zero
25 Reserved. Read returns zero
26 Reserved. Read returns zero
Fast Clearing Enable bit. Enables clearing of ready status (for both fast and slow) bit automatically
when corresponding message is read. Default value is 1. See
Status Register (FMSG_RDY)
27
(SMSG_RDY)
FAST_CLR
0 – Fast Clearing is disabled. Bits will be cleared by writing 1
1 – Fast Clearing is enabled
28 Reserved. Read returns zero
Debug Freeze. This bit will enable the debug mode support. SENT Module will freeze in debug mode
if this bit is set. Default is 0.
29
0 – No effect in debug mode
DBG_FRZ
1 – Freeze in debug mode
30 Reserved. Read returns zero
SENT Receiver Global Enable. This bit enables or disables the complete receiver module irrespective
of the setting of individual channel enable bits. User software must program all channel parameters
before setting this bit. Default is 0.
31
SENT_EN
0 – Entire module is disabled
1 – Module is enabled
49.3.2.2 Channel Enable Register (CHNL_EN)
This register is used to enable individual SENT Receiver channels in the module. The user
software must ensure all channel parameters and control settings have been programmed
before writing to this bit. In case these parameters are changed while the channel is
enabled, normal operation is not guaranteed.
Note: The following register figure and table shows the maximum possible configuration but the
exact number of valid register bits are dependent on supported SENT channels on the
device. Please see Device Configuration chapter for number of support SENT channels.
Reads of bits beyond the supported number of channels should be ignored and these bits
must be written to 0.
1368/2058
Table 790. GBL_CTRL field descriptions(Continued)
and Section 49.3.2.5: Slow Serial Message Ready Status Register
for details on the ready status bits.
DocID027809 Rev 4
Description
Section 49.3.2.4: Fast Message Ready
RM0400