STMicroelectronics SPC572L series Reference Manual page 1264

LVDS Fast Asynchronous Serial Transmission (LFAST) – Interprocessor Communications
Figure 672. Extracting Header and Payload from the 16-bit output from Auto-
16 15 14 13 12
1 0 1 0
A
1 0 0 0
0 0 0 0
0 1 0 0
C15 C14 C13 C12 C11 C10
T15
T14 T13 T12
47.7.2.3.1 Line Receiver states
The LD has the following states:
•
Shutdown
The LR enters in the shutdown state when the power down signal is high. In this state
the LR regulator is supplying a Vdd level, however the LR is not enabled. In this state
the LR holds its off value. Once power down signal is negated, a predefined settling
time is required before the LR may be used for communication. During the settling time
the peer LFAST device should not start its transfer.
• Sleep
The LR enters in the Sleep state when the sleep signal is high. In the sleep state, the
LR is enabled, but held in a power-saving state. Sleep mode may be used during inter-
frame gaps that are long compared to the frame durations but not long enough to allow
the interface(s) or high-speed clock generators to be powered down completely. In this
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11 10 9 8
1 0 0 0
8
0 1 0 0 1
1 0 0 1 0
1 0 1 1
H7
C9 C8 C7
Unsolicited Message
T11 T10 T9 T8 T7
DATA
DocID027809 Rev 4
correlation.
7 6 5 4
0 1 0 0 1
4
0 1 1
H7
1 1
H7 H6
H6 H5 H4 H3
Header
C6 C5 C4 C3 C2 C1
T6 T5 T4 T3
Updated and
shifted on every
Phase 0 clock
3 2 1
SYNC
0 1 1
B
N (4) Cycles
H6 H5 H4
N+1 (5) Cycles
H4
H5 H3
N+5 (8) Cycles
H2 H1 H0
Extract 8 LSBs
Unsolicited Data
C0
Extract all 16 bits
Slave Rx Data
T2 T1 T0
Extract 16 bits
Input Data