STMicroelectronics SPC572L series Reference Manual page 1464

LINFlexD
Field
LIN state
0: Sleep mode
LINFlexD is in Sleep mode, to save power consumption.
1: Init, 2: Idle
This mode is entered when:
– SLEEP bit and INIT bit are reset by software.
– Wakeup pulse has been received on RX pin (AUTOWU set).
– Previous frame transmission/reception has been completed/aborted.
3: Sync Break
In slave mode, a falling edge followed by a dominant state has been detected. Receiving sync
break.
In master mode, sync break transmission ongoing.
Note: In slave mode upon any error LIN state could be either Idle or Rec Break, depending on last
4: Sync Del
In Slave mode, valid Sync break has been detected (10 bit or 11 bit). Waiting for a rising edge.
In Master mode, Sync break transmission has been completed, sync delimiter transmission is
16–19
ongoing.
LINS[3:0]
5: Sync Field
In Slave mode, a valid sync Del has been detected (recessive state for at least one bit time).
Receiving sync field.
In Master mode, sync field transmission ongoing.
6: Identifier Field
In Slave mode, a valid sync field has been received. Receiving ID field.
In Master mode, identifier transmission is ongoing.
7: Header Reception/Transmission
In Slave mode, a valid header has been received and Identifier field is available in the BIDR.
In Master mode, header transmitted.
8: Data Reception/Data Transmission
In Receiver mode, reception ongoing.
In Transmitter mode, response transmission ongoing.
9: Checksum
Data transmission/reception completed, checksum transmission/reception ongoing.
In UART mode Idle, Init, Sleep, and Data Transmission/Reception states are flagged by the LIN
status bits.
Reserved
20–21
Read returns 0.
Release Message Buffer
22
0 Buffer data is free. Reset by hardware in when in Initialization mode
1 Buffer data ready to be read by software.
RMB
This bit should be cleared by software after reading the data received in the buffer.
Data Reception Buffer Not Empty Flag
This bit is set by hardware as soon as the first byte of response has been received and stored in
23
BDRL (when there is at least one data byte in reception buffer). Software should clear it after
DRBNE
reading all the buffers. This bit is also reset by hardware in Initialization mode.
This flag could be checked by software in case of a response timeout event.
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Table 828. LINSR field descriptions(Continued)
bit detected on LIN_RX. If last bit detected is dominant then Rec_Break, otherwise Idle.
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Description
RM0400