STMicroelectronics SPC572L series Reference Manual page 1070

CAN Subsystem
If the data section has been updated, a transmission is requested by an Add Request via
TXBAR[ARn]. The requested messages arbitrate internally with messages from an optional
Tx FIFO or Tx Queue and externally with messages on the CAN bus, and are sent out
according to their Message ID.
A Dedicated Tx Buffer allocates four 32-bit words in the Message RAM. Therefore the start
address of a Dedicated Tx Buffer in the Message RAM is calculated by adding four times
the transmit buffer index (0...31) to the Tx Buffer Start Address TXBC[TBSA].
44.3.13.2 Tx FIFO
Tx FIFO operation is configured by programming TXBC[TFQM] to '0'. Messages stored in
the Tx FIFO are transmitted starting with the message referenced by the Get Index
TXFQS[TFGI]. After each transmission the Get Index is incremented cyclically until the Tx
FIFO is empty. The Tx FIFO enables transmission of messages with the same Message ID
from different Tx Buffers in the order these messages have been written to the Tx FIFO. The
M_CAN calculates the Tx FIFO Free Level TXFQS[TFFL] as difference between Get and
Put Index. It indicates the number of available (free) Tx FIFO elements.
New transmit messages have to be written to the Tx FIFO starting with the Tx Buffer
referenced by the Put Index TXFQS[TFQPI]. An Add Request increments the Put Index to
the next free Tx FIFO element. When the Put Index reaches the Get Index, Tx FIFO Full
(TXFQS[TFQF] = '1') is signaled. In this case no further messages should be written to the
Tx FIFO until the next message has been transmitted and the Get Index has been
incremented.
When a single message is added to the Tx FIFO, the transmission is requested by writing a
'1' to the TXBAR bit related to the Tx Buffer referenced by the Tx FIFOs Put Index.
When multiple (n) messages are added to the Tx FIFO, they are written to n consecutive Tx
Buffers starting with the Put Index. The transmissions are then requested via TXBAR. The
Put Index is then cyclically incremented by n. The number of requested Tx buffers should
not exceed the number of free Tx Buffers as indicated by the Tx FIFO Free Level.When a
transmission request for the Tx Buffer referenced by the Get Index is cancelled, the Get
Index is incremented to the next Tx Buffer with pending transmission request and the Tx
FIFO Free Level is recalculated. When transmission cancellation is applied to any other Tx
Buffer, the Get Index and the FIFO Free Level remain unchanged.
A Tx FIFO element allocates four 32-bit words in the Message RAM. Therefore the start
address of the next available (free) Tx FIFO Buffer is calculated by adding four times the Put
Index TXFQS[TFQPI] (0...31) to the Tx Buffer Start Address TXBC[TBSA].
44.3.13.3 Tx Queue
Tx Queue operation is configured by programming TXBC[TFQM] to '1'. Messages stored in
the Tx Queue are transmitted starting with the message with the lowest Message ID
(highest priority). In case that multiple Queue Buffers are configured with the same Message
ID, the Queue Buffer with the lowest buffer number is transmitted first. New messages have
to be written to the Tx Buffer referenced by the Put Index TXFQS[TFQPI]. An Add Request
cyclically increments the Put Index to the next free Tx Buffer. In case that the Tx Queue is
full (TXFQS[TFQF] = '1'), the Put Index is not valid and no further message should be
written to the Tx Queue until at least one of the requested messages has been sent out or a
pending transmission request has been cancelled.
The application may use register TXBRP instead of the Put Index and may place messages
to any Tx Buffer without pending transmission request.
1070/2058 DocID027809 Rev 4
RM0400