STMicroelectronics ST72361 Auto Series Manuals

Manuals and User Guides for STMicroelectronics ST72361 Auto Series. We have 1 STMicroelectronics ST72361 Auto Series manual available for free PDF download: Manual

STMicroelectronics ST72361 Auto Series Manual (279 pages)

8-bit MCU for automotive with Flash or ROM, 10-bit ADC, 5 timers, SPI, LINSCI

Brand: STMicroelectronics | Category: Microcontrollers | Size: 2 MB

Table 1. Device Summary
1
Table of Contents
2
Description
19
Table 2. Product Overview
19
Figure 1. Device Block Diagram
20
Pin Description
21
Figure 2. LQFP 64-Pin Package Pinout
21
Figure 3. LQFP 44-Pin Package Pinout
22
Figure 4. LQFP 32-Pin Package Pinout
23
Table 3. Device Pin Description
24
Register and Memory Map
27
Table 4. Hardware Register Map
27
Figure 5. Memory Map
27
Flash Program Memory
30
Introduction
30
Main Features
30
Structure
30
Table 5. Sectors Available in Flash Devices
30
Read-Out Protection
31
ICC Interface
31
Figure 6. Memory Map and Sector Address
31
ICP (In-Circuit Programming)
32
Figure 7. Typical ICC Interface
32
IAP (In-Application Programming)
33
Related Documentation
33
Register Description
33
Table 6. Flash Control/Status Register Address and Reset Value
33
Central Processing Unit
34
Introduction
34
Main Features
34
CPU Registers
34
Accumulator (A)
34
Index Registers (X and Y)
34
Program Counter (PC)
34
Condition Code Register (CC)
35
Figure 8. CPU Registers
35
Table 7. Interrupt Software Priority Selection
36
Stack Pointer (SP)
37
Figure 9. Stack Manipulation Example
38
Supply, Reset and Clock Management
39
Introduction
39
Main Features
39
Phase Locked Loop
39
Figure 10. PLL Block Diagram
39
Multi-Oscillator (MO)
40
Figure 11. Clock, Reset and Supply Block Diagram
40
Reset Sequence Manager (RSM)
41
Introduction
41
Table 8. ST7 Clock Sources
41
Asynchronous External RESET Pin
42
External Power-On Reset
42
Internal Low Voltage Detector (LVD) Reset
42
Figure 12. RESET Sequence Phases
42
Figure 13. Reset Block Diagram
42
Internal Watchdog Reset
43
System Integrity Management (SI)
43
Low Voltage Detector (LVD)
43
Figure 14. Reset Sequences
43
Auxiliary Voltage Detector (AVD)
44
Figure 15. Low Voltage Detector Vs Reset
44
Low Power Modes
45
Interrupts
45
Table 9. Effect of Low Power Modes on si
45
Table 10. Interrupt Control/Wake-Up Capability
45
Figure 16. Using the AVD to Monitor VDD
45
Register Description
46
Table 11. Reset Source Flags
47
Interrupts
48
Introduction
48
Masking and Processing Flow
48
Table 12. Interrupt Software Priority Levels
49
Figure 17. Interrupt Processing Flowchart
49
Figure 18. Priority Decision Process
49
Interrupts and Low Power Modes
51
Concurrent & Nested Management
51
Figure 19. Concurrent Interrupt Management
51
Interrupt Register Description
52
CPU CC Register Interrupt Bits
52
Table 13. Interrupt Software Priority Levels
52
Figure 20. Nested Interrupt Management
52
Interrupt Software Priority Registers (ISPRX)
53
Table 14. Interrupt Priority Bits
53
Table 15. Dedicated Interrupt Instruction Set
53
Table 16. Interrupt Mapping
55
External Interrupts
56
I/O Port Interrupt Sensitivity
56
Figure 21. External Interrupt Control Bits
57
Register Description
58
Table 17. Interrupt Sensitivity - Ei3
58
Table 18. Interrupt Sensitivity - Ei2
58
Table 19. Interrupt Sensitivity - Ei1
58
Table 20. Interrupt Sensitivity - Ei0
59
Table 21. Nested Interrupts Register Map and Reset Values
60
Power Saving Modes
61
Introduction
61
Slow Mode
61
Figure 22. Power Saving Mode Transitions
61
Wait Mode
62
Figure 23. SLOW Mode Clock Transitions
62
Halt Mode
63
Figure 24. WAIT Mode Flow-Chart
63
Figure 25. HALT Timing Overview
64
Figure 26. HALT Mode Flow-Chart
64
Active Halt Mode
65
Table 22. MCC/RTC Low Power Mode Selection
65
Auto Wake-Up from Halt Mode
66
Figure 27. ACTIVE HALT Timing Overview
66
Figure 28. ACTIVE HALT Mode Flow-Chart
66
Figure 29. AWUFH Mode Block Diagram
67
Figure 30. AWUF Halt Timing Diagram
68
Figure 31. AWUFH Mode Flow-Chart
68
Register Description
69
Table 23. AWUPR Prescaler
69
Table 24. AWU Register Map and Reset Values
70
I/O Ports
71
Introduction
71
Functional Description
71
Input Modes
71
Output Modes
72
Alternate Functions
72
Table 25. DR Register Value and Output Pin Status
72
Table 26. I/O Port Mode Options
73
Figure 32. I/O Port General Block Diagram
73
Table 27. I/O Port Configurations
74
I/O Port Implementation
75
I/O Port Register Configurations
75
Standard Ports
75
Table 28. Configuration of PB7:6, PC0, PC3, PC7:5, PD3:2, PD5, PE7:0, PF7:0
75
Figure 33. Interrupt I/O Port State Transitions
75
Interrupt Ports
76
Table 29. Configuration of PA0, 2, 4, 6; PB0, 2,4; PC1; PD0,6 (with Pull-Up)
76
Table 30. Configuration of PA1, 3, 5, 7; PB1,3,5; PC2; PD1, 4, 7 (Without Pull-Up)
76
Pull-Up Input Port
77
Table 31. Configuration of PC4
77
Table 32. Port Configuration
77
Low Power Modes
78
Interrupts
78
Table 33. Effect of Low Power Modes on I/O Ports
78
Table 34. I/O Port Interrupt Control/Wake-Up Capability
78
Table 35. I/O Port Register Map and Reset Values
79
Window Watchdog (WWDG)
80
Introduction
80
Main Features
80
Functional Description
80
Figure 34. Watchdog Block Diagram
81
Using Halt Mode with the WDG
82
How to Program the Watchdog Timeout
82
Figure 35. Approximate Timeout Duration
82
Figure 36. Exact Timeout Duration (Tmin and Tmax)
83
Low Power Modes
84
Hardware Watchdog Option
84
Table 36. Effect of Low Power Modes on WDG
84
Figure 37. Window Watchdog Timing Diagram
84
Using Halt Mode with the WDG (WDGHALT Option)
85
Interrupts
85
Register Description
85
Control Register (WDGCR)
85
Window Register (WDGWR)
85
Table 37. Watchdog Timer Register Map and Reset Values
86
Main Clock Controller with Real Time Clock MCC/RTC
87
Programmable CPU Clock Prescaler
87
Clock-Out Capability
87
Real Time Clock Timer (RTC)
87
Figure 38. Main Clock Controller (MCC/RTC) Block Diagram
87
Low Power Modes
88
Interrupts
88
Register Description
88
MCC Control/Status Register (MCCSR)
88
Table 38. Effect of Low Power Modes on MCC/RTC
88
Table 39. MCC/RTC Interrupt Control Wake-Up Capability
88
Table 40. CPU Clock Frequency in SLOW Mode
89
Table 41. Time Base Selection
89
Table 42. Main Clock Controller Register Map and Reset Values
90
PWM Auto-Reload Timer (ART)
91
Introduction
91
Figure 39. PWM Auto-Reload Timer Block Diagram
91
Functional Description
92
Counter
92
Counter Clock and Prescaler
92
Counter and Prescaler Initialization
92
Output Compare Control
92
Independent PWM Signal Generation
93
Figure 40. Output Compare Control
93
Figure 41. PWM Auto-Reload Timer Function
93
Output Compare and Time Base Interrupt
94
External Clock and Event Detector Mode
94
Input Capture Function
94
Figure 42. PWM Signal from 0% to 100% Duty Cycle
94
Figure 43. External Event Detector Example (3 Counts)
94
Figure 44. Input Capture Timing Diagram, Fcounter = Fcpu
95
External Interrupt Capability
96
Figure 45. Input Capture Timing Diagram, Fcounter = Fcpu / 4
96
Figure 46. ART External Interrupt in Halt Mode
96
Register Description
97
Table 43. Counter Clock Control
97
Table 44. PWM Frequency Vs Resolution
98
Table 45. Pwmx Output Level and Polarity
99
Table 46. PWM Auto-Reload Timer Register Map and Reset Values
100
16-Bit Timer
102
Introduction
102
Main Features
102
Functional Description
103
Counter
103
Figure 47. Timer Block Diagram
104
Figure 48. 16-Bit Read Sequence: (from Counter or Alternate Counter Register)
104
External Clock
105
Input Capture
106
Figure 49. Counter Timing Diagram, Internal Clock Divided by 2
106
Figure 50. Counter Timing Diagram, Internal Clock Divided by 4
106
Figure 51. Counter Timing Diagram, Internal Clock Divided by 8
106
Procedure
107
Output Compare
108
Figure 52. Input Capture Block Diagram
108
Figure 53. Input Capture Timing Diagram
108
Procedure
109
Forced Compare Output Capability
110
Figure 54. Output Compare Block Diagram
110
One Pulse Mode
111
Figure 55. Output Compare Timing Diagram, Ftimer = Fcpu/2
111
Figure 56. Output Compare Timing Diagram, Ftimer = Fcpu/4
111
Pulse Width Modulation Mode
113
Figure 57. One Pulse Mode Timing Example
113
Figure 58. Pulse Width Modulation Mode Timing Example with 2 Output Compare Functions
113
Low Power Modes
115
Interrupts
115
Table 47. Effect of Low Power Modes on 16-Bit Timer
115
Table 48. Timer Interrupt Control and Wake-Up Capability
115
Summary of Timer Modes
116
Register Description
116
Control Register 1 (CR1)
116
Table 49. Timer Modes
116
Control Register 2 (CR2)
117
Control/Status Register (CSR)
118
Table 50. Clock Control Bits
118
Input Capture 1 High Register (IC1HR)
119
Input Capture 1 Low Register (IC1LR)
120
Output Compare 1 High Register (OC1HR)
120
Output Compare 1 Low Register (OC1LR)
120
Output Compare 2 High Register (OC2HR)
120
Output Compare 2 Low Register (OC2LR)
121
Counter High Register (CHR)
121
Counter Low Register (CLR)
121
Alternate Counter High Register (ACHR)
121
Alternate Counter Low Register (ACLR)
122
Input Capture 2 High Register (IC2HR)
122
Input Capture 2 Low Register (IC2LR)
122
Table 51. 16-Bit Timer Register Map
123
8-Bit Timer (TIM8)
124
Introduction
124
Main Features
124
Functional Description
124
Counter
124
Figure 59. Timer Block Diagram
126
Figure 60. Counter Timing Diagram, Internal Clock Divided by 2
127
Figure 61. Counter Timing Diagram, Internal Clock Divided by 4
127
Figure 62. Counter Timing Diagram, Internal Clock Divided by 8
127
Input Capture
128
Output Compare
129
Figure 63. Input Capture Block Diagram
129
Figure 64. Input Capture Timing Diagram
129
Forced Compare Output Capability
131
Figure 65. Output Compare Block Diagram
131
Figure 66. Output Compare Timing Diagram, Ftimer = Fcpu/2
131
One Pulse Mode
132
Figure 67. Output Compare Timing Diagram, Ftimer = Fcpu/4
132
Pulse Width Modulation Mode
134
Figure 68. One Pulse Mode Timing Example
134
Figure 69. Pulse Width Modulation Mode Timing Example
134
Low Power Modes
136
Interrupts
136
Table 52. Effect of Low Power Modes on TIM8
136
Table 53. TIM8 Interrupt Control and Wake-Up Capability
136
Summary of Timer Modes
137
Register Description
137
Control Register 1 (CR1)
137
Table 54. Timer Modes
137
Control Register 2 (CR2)
138
Control/Status Register (CSR)
139
Table 55. Clock Control Bits
139
Input Capture 1 Register (IC1R)
140
Output Compare 1 Register (OC1R)
140
Output Compare 2 Register (OC2R)
141
Counter Register (CTR)
141
Alternate Counter Register (ACTR)
141
Input Capture 2 Register (IC2R)
141
8-Bit Timer Register Map
142
Serial Peripheral Interface (SPI)
143
Introduction
143
Main Features
143
General Description
143
Functional Description
144
Figure 70. Serial Peripheral Interface Block Diagram
144
Slave Select Management
145
Figure 71. Single Master/ Single Slave Application
145
Figure 72. Generic SS Timing Diagram
145
Master Mode Operation
146
Master Mode Transmit Sequence
146
Figure 73. Hardware/Software Slave Select Management
146
Slave Mode Operation
147
Slave Mode Transmit Sequence
147
Clock Phase and Clock Polarity
147
Error Flags
148
Master Mode Fault (MODF)
148
Figure 74. Data Clock Timing Diagram
148
Overrun Condition (OVR)
149
Write Collision Error (WCOL)
149
Figure 75. Clearing the WCOL Bit (Write Collision Flag) Software Sequence
150
Low Power Modes
151
Table 56. Effect of Low Power Modes on SPI
151
Figure 76. Single Master / Multiple Slave Configuration
151
Interrupts
152
Register Description
152
Control Register (SPICR)
152
Table 57. SPI Interrupt Control and Wake-Up Capability
152
Control/Status Register (SPICSR)
153
Table 58. SPI Master Mode SCK Frequency
153
Data I/O Register (SPIDR)
155
Table 59. SPI Register Map and Reset Values
155
LINSCI Serial Communication Interface (LIN Master/Slave)
156
Introduction
156
SCI Features
156
LIN Features
157
General Description
157
SCI Mode - Functional Description
158
Conventional Baud Rate Generator Mode
158
Figure 77. SCI Block Diagram (in Conventional Baud Rate Generator Mode)
158
Extended Prescaler Mode
159
Serial Data Format
159
Transmitter
159
Figure 78. Word Length Programming
159
Receiver
161
Extended Baud Rate Generation
163
Receiver Muting and Wake-Up Feature
164
Figure 79. SCI Baud Rate and Extended Prescaler Block Diagram
164
Parity Control
165
Table 60. Character Formats
165
Low Power Modes
166
Interrupts
166
Table 61. Effect of Low Power Modes on SCI
166
Table 62. SCI Interrupt Control and Wake-Up Capability
166
SCI Mode Register Description
167
Status Register (SCISR)
167
Control Register 1 (SCICR1)
168
Control Register 2 (SCICR2)
169
Data Register (SCIDR)
170
Baud Rate Register (SCIBRR)
171
Table 63. PR Prescaler
171
Table 64. Transmitter Rate Divider
171
Extended Receive Prescaler Division Register (SCIERPR)
172
Table 65. Receiver Rate Divider
172
Extended Transmit Prescaler Division Register (SCIETPR)
173
LIN Mode - Functional Description
173
Entering LIN Mode
173
LIN Transmission
174
Figure 80. LIN Characters
174
LIN Reception
175
Figure 81. SCI Block Diagram in LIN Slave Mode
175
LIN Error Detection
177
Figure 82. LIN Header Reception Timeout
178
Figure 83. LIN Synch Field Measurement
179
LIN Baud Rate
180
LIN Slave Baud Rate Generation
180
LINSCI Clock Tolerance
181
Figure 84. LDIV Read / Write Operations When LDUM = 0
181
Figure 85. LDIV Read / Write Operations When LDUM = 1
181
Clock Deviation Causes
182
Figure 86. Bit Sampling in Reception Mode
182
Error Due to LIN Synch Measurement
183
Error Due to Baud Rate Quantization
183
Impact of Clock Deviation on Maximum Baud Rate
183
LIN Mode Register Description
184
Status Register (SCISR)
184
Control Register 1 (SCICR1)
185
Control Register 2 (SCICR2)
185
Control Register 3 (SCICR3)
186
Table 66. LIN Mode Configuration
186
Figure 87. LSF Bit Set and Clear
187
LIN Divider Registers
188
LIN Prescaler Register (LPR)
188
LIN Prescaler Fraction Register (LPFR)
188
Table 67. LDIV Mantissa
188
Table 68. LDIV Fraction
189
LIN Header Length Register (LHLR)
190
Table 69. LHL Mantissa Coding
190
Table 70. LHL Fraction Coding
191
Table 71. LINSCI1 Register Map and Reset Values
192
LINSCI Serial Communication Interface (LIN Master Only)
193
Introduction
193
Main Features
193
General Description
194
Functional Description
195
Figure 88. SCI Block Diagram
195
Serial Data Format
196
Transmitter
196
Figure 89. Word Length Programming
196
Receiver
198
Conventional Baud Rate Generation
200
Figure 90. SCI Baud Rate and Extended Prescaler Block Diagram
200
Extended Baud Rate Generation
201
Receiver Muting and Wake-Up Feature
201
Parity Control
202
Table 72. Frame Formats
202
Low Power Modes
203
Interrupts
203
SCI Synchronous Transmission
203
Table 73. Effect of Low Power Modes on SCI
203
Table 74. SCI Interrupt Control and Wake-Up Capability
203
Figure 91. SCI Example of Synchronous and Asynchronous Transmission
204
Figure 92. SCI Data Clock Timing Diagram (M = 0)
204
Register Description
205
Status Register (SCISR)
205
Figure 93. SCI Data Clock Timing Diagram (M = 1)
205
Control Register 1 (SCICR1)
207
Control Register 2 (SCICR2)
208
Control Register 3 (SCICR3)
209
Table 75. LIN Sync Break Duration
209
Data Register (SCIDR)
210
Table 76. SCI Clock on SCLK Pin
210
Baud Rate Register (SCIBRR)
211
Table 77. PR Prescaler
211
Table 78. Transmitter Rate Divider
211
Extended Receive Prescaler Division Register (SCIERPR)
212
Extended Transmit Prescaler Division Register (SCIETPR)
212
Table 79. Receiver Rate Divider
212
Table 80. Baud Rate Selection
213
Table 81. LINSCI2 Register Map and Reset Values
213
10-Bit A/D Converter (ADC)
214
Introduction
214
Main Features
214
Functional Description
214
Digital A/D Conversion Result
214
A/D Conversion
215
Figure 94. ADC Block Diagram
215
Changing the Conversion Channel
216
ADCDR Consistency
216
Low Power Modes
216
Interrupts
216
Register Description
216
Control/Status Register (ADCCSR)
216
Table 82. Effect of Low Power Modes on ADC
216
Table 83. A/D Clock Selection
217
Table 84. ADC Channel Selection
217
Data Register (ADCDRH)
218
Data Register (ADCDRL)
218
Table 85. ADC Register Map and Reset Values
218
Instruction Set
219
CPU Addressing Modes
219
Table 86. Addressing Mode Groups
219
Inherent
220
Table 87. CPU Addressing Mode Overview
220
Immediate
221
Direct
221
Indexed (no Offset, Short, Long)
221
Indirect (Short, Long)
221
Indirect Indexed (Short, Long)
222
Table 88. Instructions Supporting Direct, Indexed, Indirect and Indirect Indexed Addressing (Part 1)
222
Table 89. Instructions Supporting Direct, Indexed, Indirect and Indirect Indexed Addressing (Part 2)
222
Relative Mode (Direct, Indirect)
223
Instruction Groups
223
Table 90. Instruction Groups
223
Using a Prebyte
224
Electrical Characteristics
227
Parameter Conditions
227
Minimum and Maximum Values
227
Typical Values
227
Typical Curves
227
Loading Capacitor
227
Pin Input Voltage
227
Figure 95. Pin Loading Conditions
227
Absolute Maximum Ratings
228
Voltage Characteristics
228
Figure 96. Pin Input Voltage
228
Current Characteristics
229
Thermal Characteristics
229
Operating Conditions
230
General Operating Conditions
230
Operating Conditions with Low Voltage Detector (LVD)
230
Figure 97. Fcpu Maximum Vs VDD
230
Auxiliary Voltage Detector (AVD) Thresholds
231
Supply Current Characteristics
231
Figure 98. LVD Startup Behavior
231
Supply and Clock Managers
232
Table 91. Supply Current Consumption
232
On-Chip Peripherals
233
Table 92. Clock Source Current Consumption
233
Table 93. Peripheral Consumption
233
Clock and Timing Characteristics
234
Table 94. General Timings
234
Table 95. External Clock Source
234
Figure 99. Typical Application with an External Clock Source
234
Crystal and Ceramic Resonator Oscillators
235
Table 96. Oscillator Characteristics
235
Figure 100. Typical Application with a Crystal or Ceramic Resonator
235
PLL Characteristics
236
Table 97. PLL Characteristics
236
Figure 101. PLL Jitter Vs Signal Frequency (1)
236
Auto Wakeup from Halt Oscillator (AWU)
237
Memory Characteristics
237
RAM and Hardware Registers
237
Flash Memory
237
Table 98. AWU Oscillator Characteristics
237
Table 99. RAM Supply Voltage
237
Table 100. Dual Voltage Hdflash Memory
237
Figure 102. AWU Oscillator Freq. @ TA 25°C
237
EMC Characteristics
238
Functional EMS (Electromagnetic Susceptibility)
238
Electromagnetic Interference (EMI)
239
Absolute Maximum Ratings (Electrical Sensitivity)
239
Table 101. EMS Test Results
239
Table 102. EMI Emissions
239
Table 103. Absolute Maximum Ratings
240
Table 104. Electrical Sensitivities
240
I/O Port Pin Characteristics
241
General Characteristics
241
Table 105. I/O Characteristics
241
Figure 103. Connecting Unused I/O Pins
242
Figure 104. RPU Vs VDD with VIN = VSS
242
Figure 105. IPU Vs VDD with VIN = VSS
242
Output Driving Current
243
Table 106. Output Driving Current
243
Figure 106. Typical VOL at VDD = 5V (Standard)
243
Figure 107. Typical VOL at VDD = 5V (High-Sink)
243
Figure 108. Typical VOH at VDD = 5V
244
Figure 109. Typical VOL Vs VDD (Standard I/Os)
244
Figure 110. Typical VOL Vs VDD (High-Sink I/Os)
244
Control Pin Characteristics
245
Asynchronous RESET Pin
245
Table 107. RESET Pin Characteristics
245
Figure 111. Typical VOH Vs VDD
245
Figure 112. RESET Pin Protection When LVD Is Disabled
246
Figure 113. RESET Pin Protection When LVD Is Enabled
246
ICCSEL/ VPP Pin
247
Table 108. ICCSEL/V
247
Figure 114. RESET RPU Vs VDD
247
Figure 115. Two Typical Applications with ICCSEL/VPP Pin
247
Timer Peripheral Characteristics
248
Table 109. 8-Bit PWM-ART Auto Reload Timer Characteristics
248
Table 110. 8-Bit Timer Characteristics
248
Table 111. 16-Bit Timer Characteristics
248
Communication Interface Characteristics
250
SPI - Serial Peripheral Interface
250
Table 112. SPI Characteristics
250
Figure 116. SPI Slave Timing Diagram with CPHA = 0
251
Figure 117. SPI Slave Timing Diagram with CPHA = 1
251
10-Bit ADC Characteristics
252
Table 113. ADC Characteristics
252
Figure 118. SPI Master Timing Diagram
252
Figure 119. RAIN Max Vs Fadc with CAIN = 0Pf
253
Figure 120. Recommended CAIN/RAIN Values
253
Figure 121. Typical Application with ADC
253
Figure 122. Power Supply Filtering
254
Table 114. ADC Accuracy with F CPU = 8 Mhz, F ADC = 4 Mhz RAIN < 10Kw, VDD = 5V
255
Figure 123. ADC Accuracy
256
Package Characteristics
257
Ecopack
257
Package Mechanical Data
257
Figure 124. 32-Pin Low Profile Quad Flat Package (7X7)
257
Figure 125. 44-Pin Low Profile Quad Flat Package (10X10)
258
Figure 126. 64-Pin Low Profile Quad Flat Package (10 X10)
258
Thermal Characteristics
259
Packaging for Automatic Handling
259
Figure 127. Pin 1 Orientation in Tape and Reel Conditioning
259
Device Configuration and Ordering Information
260
Introduction
260
Flash Devices
260
Flash Configuration
260
Table 115. Package Selection
261
Table 116. Alternate Function Remapping 1
262
Table 117. Alternate Function Remapping 0
262
Table 118. OSCTYPE Selection
262
Table 119. OSCRANGE Selection
262
Flash Ordering Information
264
Figure 128. St72F361Xx-Auto Flash Commercial Product Structure
264
Transfer of Customer Code
265
Figure 129. St72P361Xxx-Auto Fastrom Commercial Product Structure
265
Figure 130. St72361Xx-Auto ROM Commercial Product Structure
266
Development Tools
268
Important Notes
269
All Devices
269
RESET Pin Protection with LVD Enabled
269
Clearing Active Interrupts Outside Interrupt Routine
269
External Interrupt Missed
270
Unexpected Reset Fetch
272
Header Time-Out Does Not Prevent Wake-Up from Mute Mode
272
Flash/Fastrom Devices Only
273
LINSCI Wrong Break Duration
273
Figure 131. Header Reception Event Sequence
273
Figure 132. LINSCI Interrupt Routine
273
16-Bit and 8-Bit Timer PWM Mode
275
ROM Devices Only
275
16-Bit Timer PWM Mode Buffering Feature Change
275
Revision History
276
Table 120. Document Revision History
277

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