STMicroelectronics STM32F05 series Manuals

Manuals and User Guides for STMicroelectronics STM32F05 series. We have 1 STMicroelectronics STM32F05 series manual available for free PDF download: Reference Manual

STMicroelectronics STM32F05 series Reference Manual (742 pages)

advanced ARM-based 32-bit MCUs

Brand: STMicroelectronics | Category: Microcontrollers | Size: 10.58 MB

Table 1. Applicable Products
1
- Table of Contents
  2
- SYSCFG External Interrupt Configuration Register
  4
Documentation Conventions

34
- List of Abbreviations for Registers
  34
- Glossary
  34
- Peripheral Availability
  34
System and Memory Overview

35
- System Architecture
  35
- Figure 1. System Architecture
  35
- Memory Organization
  37
- Embedded SRAM
  40
- Flash Memory Overview
  40
- Boot Configuration
  40
- Table 3. Boot Modes
  40
Embedded Flash Memory

42
Option Byte Description

59
Cyclic Redundancy Check Calculation Unit (CRC)

62
- Introduction
  62
- CRC Main Features
  62
- CRC Functional Description
  63
- Figure 5. CRC Calculation Unit Block Diagram
  63
- CRC Registers
  64
Power Control (PWR)

67
- Power Supplies
  67
- Power Supply Supervisor
  69
- Low-Power Modes
  71
  - Slowing down System Clocks
    71
  - Table 13. Low-Power Mode Summary
    71
  - Peripheral Clock Gating
    72
  - Sleep Mode
    72
  - Stop Mode
    73
  - Table 14. Sleep-Now
    73
  - Table 15. Sleep-On-Exit
    73
  - Standby Mode
    74
  - Table 16. Stop Mode
    74
  - Table 17. Standby Mode
    75
  - Auto-Wakeup from Low-Power Mode
    76
- Power Control Registers
  77
Reset and Clock Control (RCC)

82
- Reset
  82
  - System Reset
    82
  - Figure 9. Simplified Diagram of the Reset Circuit
    82
  - Power Reset
    83
  - Backup Domain Reset
    83
- Clocks
  83
  - Figure 10. Clock Tree
    85
  - Figure 11. HSE/ LSE Clock Sources
    86
  - HSE Clock
    86
  - HSI Clock
    87
  - LSE Clock
    88
  - LSI Clock
    88
  - Pll
    88
  - ADC Clock
    89
  - Clock Security System (CSS)
    89
  - System Clock (SYSCLK) Selection
    89
  - Clock-Out Capability
    90
  - RTC Clock
    90
  - Watchdog Clock
    90
- Low Power Modes
  90
- RCC Registers
  92
General-Purpose I/Os (GPIO)

118
System Configuration Controller (SYSCFG)

135
- SYSCFG Registers
  135
  - SYSCFG Configuration Register 1 (SYSCFG_CFGR1)
    135
  - SYSCFG External Interrupt Configuration Register 1
    136
    
    (Syscfg_Exticr1)
    136
  - SYSCFG External Interrupt Configuration Register 2
    138
    
    (Syscfg_Exticr2)
    138
    
    (Syscfg_Exticr3)
    138
    
    (Syscfg_Exticr4)
    139
  - SYSCFG Configuration Register 2 (SYSCFG_CFGR2)
    139
  - SYSCFG Register Maps
    140
  - Table 22. SYSCFG Register Map and Reset Values
    140
Direct Memory Access Controller (DMA)

142
- DMA Introduction
  142
- DMA Main Features
  142
- DMA Functional Description
  143
  - DMA Transactions
    143
  - Figure 18. DMA Block Diagram
    143
  - Arbiter
    144
  - DMA Channels
    144
  - Programmable Data Width, Data Alignment and Endians
    146
  - Table 23. Programmable Data Width & Endian Behavior (When Bits PINC = MINC = 1)
    146
  - Error Management
    147
  - Interrupts
    147
  - DMA Request Mapping
    147
  - Table 24. DMA Interrupt Requests
    147
  - Figure 19. DMA Request Mapping
    148
  - Table 25. Summary of DMA Requests for each Channel
    149
- DMA Registers
  150
Interrupts and Events

157
Analog-To-Digital Converter (ADC)

168
Digital-To-Analog Converter (DAC1)

205
- DAC1 Introduction
  205
- DAC1 Main Features
  205
- Single Mode Functional Description
  206
  - DAC Channel Enable
    206
  - Table 39. DAC1 Pins
    206
  - Figure 38. DAC1 Block Diagram
    206
  - DAC Output Buffer Enable
    207
  - DAC Data Format
    207
  - DAC Conversion
    207
  - Figure 39. Data Registers in Single DAC Channel Mode
    207
  - DAC Output Voltage
    208
  - DAC Trigger Selection
    208
  - Table 40. External Triggers
    208
  - Figure 40. Timing Diagram for Conversion with Trigger Disabled TEN = 0
    208
- DMA Request
  209
- DAC Registers
  209
Comparator (COMP)

215
- COMP Introduction
  215
- COMP Main Features
  215
- COMP Functional Description
  216
  - General Description
    216
  - Clock
    216
  - Comparator Inputs and Output
    216
  - Figure 41. Comparators Block Diagram
    216
  - Interrupt and Wakeup
    217
  - Power Mode
    217
  - Comparator LOCK Mechanism
    217
  - Hysteresis
    217
  - Figure 42. Comparator Hysteresis
    218
- COMP Registers
  219
Advanced-Control Timers (TIM1)

223
General-Purpose Timers (TIM2 and TIM3)

292
General-Purpose Timer (TIM14)

353
General-Purpose Timers (TIM15/16/17)

375
Basic Timer (TIM6)

440
Infrared (IRTIM) Interface

452
- Main Features
  452
- Figure 191. IR Internal Hardware Connections with TIM16 and TIM17
  452
Independent Watchdog (IWDG)

453
- Introduction
  453
- IWDG Main Features
  453
- IWDG Functional Description
  453
  - Window Option
    453
  - Hardware Watchdog
    454
  - Register Access Protection
    454
  - Debug Mode
    454
- IWDG Registers
  455
  - Key Register (IWDG_KR)
    455
  - Figure 192. Independent Watchdog Block Diagram
    455
  - Prescaler Register (IWDG_PR)
    456
  - Reload Register (IWDG_RLR)
    457
  - Status Register (IWDG_SR)
    458
  - Window Register (IWDG_WINR)
    459
  - IWDG Register Map
    460
  - Table 59. IWDG Register Map and Reset Values
    460
System Window Watchdog (WWDG)

461
- WWDG Introduction
  461
- WWDG Main Features
  461
- WWDG Functional Description
  461
- Figure 193. Watchdog Block Diagram
  462
- How to Program the Watchdog Timeout
  463
- Figure 194. Window Watchdog Timing Diagram
  463
- Debug Mode
  464
- WWDG Registers
  465
  - Control Register (WWDG_CR)
    465
  - Configuration Register (WWDG_CFR)
    466
  - Status Register (WWDG_SR)
    466
  - WWDG Register Map
    467
  - Table 60. WWDG Register Map and Reset Values
    467
Inter-Integrated Circuit (I 2 C) Interface

468
Real-Time Clock (RTC)

535
- Introduction
  535
- RTC Main Features
  535
- RTC Functional Description
  536
  - RTC Block Diagram
    536
  - Figure 227. RTC Block Diagram
    536
  - Gpios Controlled by the RTC
    537
  - Table 77. RTC Pin PC13 Configuration
    537
  - Clock and Prescalers
    538
  - Table 78. LSE Pin PC14 Configuration
    538
  - Table 79. LSE Pin PC15 Configuration
    538
  - Real-Time Clock and Calendar
    539
  - Programmable Alarm
    539
  - RTC Initialization and Configuration
    540
  - Reading the Calendar
    541
  - Resetting the RTC
    542
  - RTC Synchronization
    542
  - RTC Reference Clock Detection
    543
  - RTC Smooth Digital Calibration
    544
  - Time-Stamp Function
    546
  - Tamper Detection
    546
  - Calibration Clock Output
    548
  - Alarm Output
    548
- RTC Low Power Modes
  548
- Table 80. Effect of Low Power Modes on RTC
  548
- RTC Interrupts
  549
- Table 81. Interrupt Control Bits
  549
- RTC Registers
  550
Universal Synchronous Asynchronous Receiver Transmitter (USART)

571
Serial Peripheral Interface / Inter-IC Sound (SPI/I2S)

634
Touch Sensing Controller (TSC)

681
HDMI-CEC Controller (HDMI-CEC)

699
- Introduction
  699
- HDMI-CEC Controller Main Features
  699
- HDMI-CEC Functional Description
  700
  - HDMI-CEC Pin
    700
  - Table 102. HDMI Pin
    700
  - Figure 289. Block Diagram
    700
  - Message Description
    701
  - Bit Timing
    701
  - Figure 290. Message Structure
    701
  - Figure 291. Blocks
    701
- Arbitration
  702
  - Figure 292. Bit Timings
    702
  - Figure 293. Signal Free Time
    702
  - Figure 294. Arbitration Phase
    702
  - Figure 295. SFT of Three Nominal Bit Periods
    703
  - SFT Option Bit
    703
- Error Handling
  704
  - Bit Error
    704
  - Message Error
    704
  - Bit Rising Error (BRE)
    704
  - Figure 296. Error Bit Timing
    704
  - Short Bit Period Error (SBPE)
    705
  - Long Bit Period Error (LBPE)
    705
  - Figure 297. Error Handling
    705
  - Table 103. Error Handling Timing Parameters
    706
  - Transmission Error Detection (TXERR)
    707
  - Table 104. TXERR Timing Parameters
    707
  - Figure 298. TXERR Detection
    707
- HDMI-CEC Interrupts
  708
- Table 105. HDMI-CEC Interrupts
  708
- HDMI-CEC Registers
  709
Debug Support (DBG)

718
- Overview
  718
- Reference ARM Documentation
  719
- Pinout and Debug Port Pins
  719
  - SW Debug Port Pins
    720
  - Flexible SW-DP Pin Assignment
    720
  - Internal Pull-Up & Pull-Down on SW Pins
    720
- ID Codes and Locking Mechanism
  720
  - Table 107. SW Debug Port Pins
    720
  - MCU Device ID Code
    721
- SW Debug Port
  721
  - SW Protocol Introduction
    721
  - SW Protocol Sequence
    722
  - Table 108. Packet Request (8-Bits)
    722
  - Table 109. ACK Response (3 Bits)
    722
  - Table 110. DATA Transfer (33 Bits)
    722
  - SW-DP State Machine (Reset, Idle States, ID Code)
    723
  - DP and AP Read/Write Accesses
    723
  - SW-DP Registers
    723
  - Table 111. SW-DP Registers
    723
  - SW-AP Registers
    725
- Core Debug
  725
- Table 112. 32-Bit Debug Port Registers Addressed through the Shifted Value A[3:2]
  725
- Table 113. Core Debug Registers
  725
- BPU (Break Point Unit)
  726
  - BPU Functionality
    726
- DWT (Data Watchpoint)
  726
  - DWT Functionality
    726
  - DWT Program Counter Sample Register
    726
- MCU Debug Component (DBGMCU)
  726
Device Electronic Signature

733
- Unique Device ID Register (96 Bits)
  733
- Memory Size Data Register
  735
  - Flash Size Data Register
    735
Revision History

741
- Table 115. Document Revision History
  741

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STMicroelectronics STM32F05 series Manuals

STMicroelectronics STM32F05 series Reference Manual (742 pages)

Table of Contents

Documentation Conventions

System and Memory Overview

Embedded Flash Memory

Option Byte Description

Cyclic Redundancy Check Calculation Unit (CRC)

Power Control (PWR)

Reset and Clock Control (RCC)

General-Purpose I/Os (GPIO)

System Configuration Controller (SYSCFG)

Direct Memory Access Controller (DMA)

Interrupts and Events

Analog-To-Digital Converter (ADC)

Digital-To-Analog Converter (DAC1)

Comparator (COMP)

Advanced-Control Timers (TIM1)

General-Purpose Timers (TIM2 and TIM3)

General-Purpose Timer (TIM14)

General-Purpose Timers (TIM15/16/17)

Basic Timer (TIM6)

Infrared (IRTIM) Interface

Independent Watchdog (IWDG)

System Window Watchdog (WWDG)

Inter-Integrated Circuit (I 2 C) Interface

Real-Time Clock (RTC)

Universal Synchronous Asynchronous Receiver Transmitter (USART)

Serial Peripheral Interface / Inter-IC Sound (SPI/I2S)

Touch Sensing Controller (TSC)

HDMI-CEC Controller (HDMI-CEC)

Debug Support (DBG)

Device Electronic Signature

Revision History

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