STMicroelectronics SPC572L series Reference Manual page 1121

RM0400
Field
Send Trigger Command. A Trigger Command requires that only this bit to be set by software, the
15 trigger does not depend on settings in the SIPI_CAR.
TC 0 Trigger command not sent
1 Trigger command sent
16–23 Reserved
Word Length Transfer. For Streaming write WL bits should be written 10.
00 8-bit
24–25
01 16-bit
WL[1:0]
10 32-bit
11 not used
Channel Enable. If all the channel enables are enabled simultaneously, channel 0 will be given the
26 highest priority for transmission. For channels, the lowest channel number is given highest priority.
CHEN 0 Channel is disabled
1 Channel is enabled
Streaming Transfer. This bit is hard-coded to 0 for channels 0, 1 and 3. It can only be written for
27 channel 2 (SIPI_CCR2). This bit can only be written when SIPI_CCRn[WRT] = 1.
ST 0 Streaming transfer is disabled
1 Streaming transfer is enabled
ID Read Request Transfer. This request returns the value of the CHIP ID.
28
0 ID read request not sent
IDT
1 ID read request sent
Read Request Transfer.
29
0 Read request will not be sent
RRT
1 Read request transfer by the initiator. This bit cannot be written if SIPI_CCRn[IDT] = 1.
Write Request Transfer.
30
0 No write request will be sent
WRT 1 Write request transfer by the initiator. This bit cannot be written if SIPI_CCRn[IDT] = 1 or
SIPI_CCRn[RRT] = 1.
DMA Enable. When enabling DMA mode, this bit should be set by software. It will then be cleared
31 by hardware after one major loop has completed.
DEN 0 Channel will be used for bus interface access
1 Channel will be used for DMA access
45.15.1.2 SIPI Channel Status Register (SIPI_CSRn)
The SIPI_CSRn contains the status bits for the current transfer.
Table 594. SIPI_CCRn field descriptions(Continued)
DocID027809 Rev 4
Serial Interprocessor Interface (SIPI)
Description
1121/2058
1133