STMicroelectronics SPC572L series Reference Manual page 1343

RM0400
Table 781. Receive Buffer Descriptor field descriptions(Continued)
Word Field
Offset + 0 RO2
Offset + 0 L
Offset + 0 M
Offset + 0 BC
Offset + 0 MC
Offset + 0 LG
Offset + 0 NO
Offset + 0 CR
Offset + 0 OV
Offset + 0 TR
Data
Offset + 2
Length
0ffset + 4 A[31:16]
Offset + 6 A[15:0]
1. The receive buffer pointer, containing the address of the associated data buffer, must always be evenly divisible by 16. The
buffer must reside in memory external to the FEC. The Ethernet controller never modifies this value.
Note: When the software driver sets an E bit in one or more receive descriptors, the driver should
follow with a write to RDAR.
48.5.3.3 Ethernet Transmit Buffer Descriptor (TxBD)
Data is presented to the FEC for transmission by arranging it in buffers referenced by the
channel's TxBDs. The Ethernet controller confirms transmission by clearing the ready bit
(TxBD[R]) when DMA of the buffer is complete. In the TxBD, the user initializes the R, W, L,
and TC bits and the length (in bytes) in the first longword and the buffer pointer in the
second longword.
Receive software ownership. This field is reserved for use by software. This read/write bit
is not modified by hardware, nor does its value affect hardware.
Last in frame. Written by the FEC.
0 The buffer is not the last in a frame.
1 The buffer is the last in a frame.
Miss. Written by the FEC. This bit is set by the FEC for frames accepted in promiscuous
mode, but flagged as a miss by the internal address recognition. Therefore, while in
promiscuous mode, you can use the M-bit to quickly determine whether the frame was
destined to this station. This bit is valid only if the L-bit is set and the PROM bit is set.
0 The frame was received because of an address recognition hit.
1 The frame was received because of promiscuous mode.
Set if the DA is broadcast (FFFF_FFFF_FFFF).
Set if the DA is multicast and not BC.
Rx frame length violation. Written by the FEC. A frame length greater than
RCR[MAX_FL] was recognized. This bit is valid only if the L-bit is set. The receive data is
not altered in any way unless the length exceeds 2047 bytes.
Receive non-octet aligned frame. Written by the FEC. A frame that contained a number
of bits not divisible by 8 was received, and the CRC check that occurred at the preceding
byte boundary generated an error. This bit is valid only if the L-bit is set. If this bit is set,
the CR bit is not set.
Receive CRC error. Written by the FEC. This frame contains a CRC error and is an
integral number of octets in length. This bit is valid only if the L-bit is set.
Overrun. Written by the FEC. A receive FIFO overrun occurred during frame reception. If
this bit is set, the other status bits, M, LG, NO, CR, and CL lose their normal meaning and
are zero. This bit is valid only if the L-bit is set.
Set if the receive frame is truncated (frame length > 2047 bytes). If the TR bit is set, the
frame must be discarded and the other error bits must be ignored as they may be
incorrect.
Data length. Written by the FEC. Data length is the number of octets written by the FEC
into this BD's data buffer if L equals 0 (the value is equal to EMRBR), or the length of the
frame including CRC if L is set. It is written by the FEC once as the BD is closed.
RX data buffer pointer, bits [31:16]
RX data buffer pointer, bits [15:0]
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Fast Ethernet Controller (FEC)
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