STMicroelectronics SPC572L series Reference Manual page 1198

Deserial Serial Peripheral Interface (DSPI)
Figure 623. DSPI Modified Transfer Format (MTFE = 1, CPHA = 0, f
protocol
clk
PCS
SIN
t
SCK
SOUT
46.5.6.4 Modified SPI/DSI Transfer Format (MTFE = 1, CPHA = 1)
The following figures show the Modified Transfer Format for CPHA = 1. Only the condition,
where CPOL = 0 is shown. At the start of a transfer the DSPI asserts the PCS signal to the
slave device. After the PCS to SCK delay has elapsed the master and the slave put data on
their SOUT pins at the first edge of SCK. The slave samples the master SOUT signal on the
even numbered edges of SCK. The master samples the slave SOUT signal on the odd
numbered SCK edges starting with the third SCK edge. The slave samples the last bit on
the last edge of the SCK. The master samples the last slave SOUT bit one half SCK cycle
after the last edge of SCK. No clock edge will be visible on the master SCK pin during the
sampling of the last bit. The SCK to PCS delay must be greater or equal to half of the
SCK period.
Figure 624. DSPI Modified Transfer Format (MTFE = 1, CPHA = 1, f
protocol
clk
PCS
SIN
SCK
SOUT
1198/2058
DSPI samples SIN
t
vd_sl
D0 D1
Slave samples SOUT
CSC
D0 D1
DSPI samples SIN
t
vd_sl
D0
Slave samples SOUT
t
CSC
1 3
2 4
D0
t
hd_ms
t
su_ms
D2
t t
su_sl hd_sl
D2
t
hd_ms
t
su_ms
D1 D2
7
5
6
t
hd_sl
t
su_sl
D1 D2
DocID027809 Rev 4
Dn
Dn
t
ASC
Dn
2n+1 2n+2
8
Dn
RM0400
= f /3)
sck p
t
ASC
= f /2)
sck p