STMicroelectronics SPC572L series Reference Manual page 1275

RM0400 LVDS Fast Asynchronous Serial Transmission (LFAST) – Interprocessor Communica-
The exit from this mode happens on reception of Test mode off ICLC command.
47.7.6.3.2.6 Loopback payload on ICLC
This ICLC command is decoded and TMCR[LPON] = 1 to indicate to the Tx Block that the
received payload is to be sent back. The exit from this mode happens on reception of Test
mode off ICLC command. The Rx interface causes RIISR[ICLPF] = 1 on reception of this
ICLC command.
47.7.6.3.2.7 Test mode off ICLC
This ICLC command is decoded and TMCR[LPON] and TMCR[CLKTST] are cleared to
indicate to the Tx block to exit from loopback mode or clock test mode.
Another option is for the payload loopback option to remain enabled until negated on the
toggling of LFAST interface enable .
47.7.6.3.2.8 Ping response ICLC
The LFAST master considers any ICLC frame payload as ping response data. The LFAST
masters Rx block will store the received ping data in PISR[RXPNGD] and match it with
PICR[PNGPYLD]. RIISR[ICPSF] = 1 if the Ping received matches with the one stored in
PICR[PNGPYLD], or RIISR[ICPFF] = 1.
47.7.6.4 CTS flow
47.7.6.4.1 CTS Tx flow
The CTS frame, if enabled by the S/W, indicates the status of the Receive Data FIFO. CTS
frame is triggered whenever Rx Data FIFO reaches either the High/Low threshold and no
data, ICLC or unsolicited frame is ready for transmission.
Programing model for CTS frame transmit:
•
Program RFCR[CTSMX] and RFCR[CTSMN].
•
Enable the CTS frame Transmission by programming MCR[CTSEN] = 1.
•
Program MCR[TXEN] = 1 and MCR[DRFEN] = 1 to enable the Tx path.
•
The CTS bit sent with a valid frame (for example, data, ICLC and unsolicited) is 1 until
the Rx Data FIFO reaches High Threshold.
•
When the Rx Data FIFO reaches higher threshold and no valid frame (data, ICLC and
unsolicited) is pending for transmission, then the CTS frame is triggered, with CTS bit
of header = 0 and the status bit RISR[RXMXF] = 1.
•
When the Rx Data FIFO reaches Low Threshold, due to system side reads and no
valid frame (data, ICLC and unsolicited) is pending for transmission, then the CTS
frame is triggered, with CTS bit of header = 1, and status bit RISR[RXMNF] = 1.
47.7.6.4.2 CTS Rx flow
Whenever a CTS frame header or any other frame with valid header is received with CTS
bit = 0, then RISR[RXCTSF] = 1. The Tx Interface arbitration for unsolicited frame and data
frame transmit request is turned off on reception of frame with CTS bit 0. The arbitration for
unsolicited frame and data frame is enabled on reception of frame with CTS bit 1. Frame
with LCT type CTS are not stored in the LFAST.
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