STMicroelectronics SPC572L series Reference Manual page 1010

CAN Subsystem
Table 531. CC Control Register field descriptions(Continued)
Field
ASM Restricted Operation Mode
The Restricted Operation Mode is intended for applications that adapt themselves to different CAN
bit rates. The application tests different bit rates and leaves the Restricted Operation Mode after it
has received a valid frame. In the optional Restricted Operation Mode the node is able to transmit
and receive data and remote frames and it gives acknowledge to valid frames, but it does not send
active error frames or overload frames. In case of an error condition or overload condition, it does
not send dominant bits, instead it waits for the occurrence of bus idle condition to resynchronize
29 itself to the CAN communication. The error counters are not incremented. Bit ASM can only be set
by the Host when both CCE and INIT are set to '1'. The bit can be reset by the Host at any time.
ASM
If the M_CAN is connected to a Clock Calibration on CAN unit, ASM is controlled by input M_CAN
calibration OK (m_can_cok) signal. In case m_can_cok switches to '0', bit ASM is set. When
m_can_cok switches back to '1', bit ASM returns to the previously written value. The state of ASM is
the written value while input m_can_cok is at '1'. The input is hardwired to '1' when there is no Clock
Calibration on CAN unit connected.
0 Normal CAN operation
1 Restricted Operation Mode active
Configuration Change Enable
30
0 The CPU has no write access to the protected configuration registers
CCE
1 The CPU has write access to the protected configuration registers (while CCCR.INIT = '1')
Initialization
31
0 Normal Operation
INIT
1 Initialization is started
Note: Due to the synchronization mechanism between the two clock domains, there may be a
delay until the value written to INIT can be read back. Therefore the programmer has to
ensure that the previous value written to INIT has been accepted by reading INIT before
setting INIT to a new value.
44.3.5.2.7 Bit Timing and Prescaler Register (BTP)
This register is only writable if bits CCCR[CCE] and CCCR[INIT] are set. The CAN bit time
may be programed in the range of [4...81] time quanta. The CAN time quantum may be
programmed in the range of [1...1024] M_CAN clock periods.
Equation 22 tq = (BRP + 1) M_CAN clock period
TSEG1 is the sum of Prop_Seg and Phase_Seg1. TSEG2 is Phase_Seg2.
Therefore the length of the bit time is (prog rammed values) [TSEG1 + TSEG2 + 3] tq or
(functional values) [Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2] tq.
The Information Processing Time (IPT) is zero, meaning the data for the next bit is available
at the first clock edge after the sample point.
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Description
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