STMicroelectronics SPC572L series Reference Manual page 1400

SENT Receiver (SRX)
49.4.2.2 DMA request for Slow Serial Message reading
A separate DMA request (different from DMA request for Fast Message) is generated for all
slow serial messages received on all channels. The data flow will happen as follows:
•
Request will be asserted when any of the DMA enabled channels has successfully
received one complete serial message (short or enhanced) and kept asserted till all
messages have been read from their respective memory-mapped registers
• Similar to DMA read for Fast Messages, data for slow serial messages will be read
from DMA Slow Serial Message Read register set in memory map, the register set
comprising of:
–
–
–
• A fixed round robin sequencing logic will be running and it will update the DMA Slow
Serial Message Read register set for DMA read and move to the next channel when
this message is read out completely (i.e., 3 DMA read accesses to the above
mentioned registers)
• The channel number and time stamp will also be appended for every message
•
A message type bit (TYPE) will also be appended to distinguish between short and
enhanced serial messages
•
The DMA controller should be programmed to read only one message in one DMA
transfer (i.e. 12 bytes). If it is programmed to read more than one message in one DMA
transfer, underflow in buffers might occur
• Since serial messages receive rate is very slow, user software should ensure there is
no overflow
•
The fixed round robin sequence logic for DMA read is the same as that used for Fast
Messages (see
Figure 799
read is done on DMA Slow Serial Message Read register set.
1400/2058
Section 49.3.2.15: DMA Slow Serial Message Bit3 Read Register
(DMA_SMSG_BIT3)
Section 49.3.2.16: DMA Slow Serial Message Bit2 Read Register
(DMA_SMSG_BIT2)
Section 49.3.2.17: DMA Slow Serial Message Time Stamp Read Register
(DMA_SMSG_TS)
Section 49.4.2.1: DMA request for Fast Message reading
shows the sequencing of channels for serial messages to be read when DMA
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