STMicroelectronics SPC572L series Reference Manual page 1271

RM0400 LVDS Fast Asynchronous Serial Transmission (LFAST) – Interprocessor Communica-
MCR[DATAEN], MCR[DRFEN] and MCR[TXEN] bits, should be set to enable the transfer of
Tx data.
If MCR[DATAEN] = 0, then the valid frames in the in Tx data FIFO will be ignored for
transmission. The Payload Size and channel type of each frame is specified by the System
Side Module interface during transfer of the frame to the LFAST interface. The frame header
is stored in the Tx packet FIFO and the payload in the Tx data FIFO.Whenever the Tx FIFO
has at least one frame then a data transmit request is made to the Tx arbiter of the LFAST.
Tx block arbitrates the data transmit request and schedules it depending on the priority of all
the pending transmit requests. When data request is scheduled by Tx block, the required
data is fetched from Tx data FIFO. The number of frames present in the Tx FIFO for
transmission is indicated by the bitfield DFSR[TXFCNT].
47.7.6.1.1.1 Programing model for Tx data transmit
1. Program MCR[DATAEN] = 1, MCR[TXEN] = 1 and MCR[DRFEN] = 1 to enable the Tx
path of LFAST device.
2. Select the desired clock rate at which data should be transmitted, using ICLC transfers
and appropriate programing of SCR[TDR] bits.
3. Frame present in TX FIFO (Data and Packet FIFO) are sent.
4. TISR[TXDTF] = 1 after each frame transfer.
5. CTS is set depending on the push/pull mode setting defined by MCR[CTSEN].
47.7.6.1.2 Data receive
LFAST master and slave supports reception of data frame. The received frame is
determined to be of data frame type by decoding channel type field of the header present in
the received frame. The MCR[DATAEN], MCR[RXEN] and MCR[DRFEN] bits should be set
to enable the data frame reception.When MCR[DATAEN] = 0 the received data frames will
be ignored and will not be placed in the Rx data FIFO.
The Rx data frames received by Rx block are stored in the Rx FIFO. Whenever the frame is
received in the Rx FIFO the System Side Module is indicated by assertion of LFAST Rx
FIFO ready signal. The frame size and the Channel type is passed to the LFAST. The frame
boundaries are indicated by start of frame and end of frame signals. The number of unread
frames in the Rx Data FIFO are indicated by DFSR[RXFCNT]. When Rx DATA FIFO is full
and cannot accommodate current frame completely, then the remaining data of the Rx
frame is discarded. In this case, UNSRSR[RXOF] = 1 and an interrupt is generated if the
RIER[RXOFIE] = 1.
47.7.6.2 Unsolicited flow
47.7.6.2.1 Unsolicited frame transmit flow
The S/W is the initiator for unsolicited frames to the LFAST peer device. The unsolicited
frame header and payload is programed into the Unsolicited Data and Control registers.
Once the Payload is programed UNSTCR[USNDRQ] is set, generating a request for
unsolicited frame transfer to the Tx arbiter.
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