STMicroelectronics SPC572L series Reference Manual page 1341

RM0400
or may rely on the buffer/frame interrupts. The driver may process these buffers, and they
can return to the free list.
The ECR[ETHER_EN] bit operates as a reset to the BD/DMA logic. When
ECR[ETHER_EN] is cleared, the DMA engine BD pointers are reset to point to the starting
transmit and receive BDs. The buffer descriptors are not initialized by hardware during
reset. At least one transmit and receive buffer descriptor must be initialized by software
before ECR[ETHER_EN] is set.
The buffer descriptors operate as two separate rings. ERDSR defines the starting address
for receive BDs and ETDSR defines the starting address for transmit BDs. The wrap (W) bit
defines the last buffer descriptor in each ring. When W is set, the next descriptor in the ring
is at the location pointed to by ERDSR and ETDSR for the receive and transmit rings,
respectively. Buffer descriptor rings must start on a 32-bit boundary; however, it is
recommended they be 128-bit aligned.
48.5.3.1.1 Driver/DMA operation with transmit BDs
Typically, a transmit frame is divided between multiple buffers. An example is to have an
application payload in one buffer, TCP header in a second buffer, IP header in a third buffer,
and Ethernet/IEEE 802.3 header in a fourth buffer. The Ethernet MAC does not prepend the
Ethernet header (destination address, source address, length/type field(s)), so the driver
must provide this in one of the transmit buffers. The Ethernet MAC can append the Ethernet
CRC to the frame. TxBD[TC], which must be set by the driver, determines whether the MAC
or driver appends the CRC.
The driver (TxBD software producer) should set up Tx BDs so a complete transmit frame is
given to the hardware at once. If a transmit frame consists of three buffers, the BDs should
be initialized with pointer, length, and control (W, L, TC, ABC) and then the TxBD[R] bit
should be set in reverse order (third, second, then first BD) to ensure that the complete
frame is ready in memory before the DMA begins. If the TxBDs are set up in order, the DMA
controller could DMA the first BD before the second was made available, potentially causing
a transmit FIFO underrun.
In the FEC, the driver notifies the DMA that new transmit frame(s) are available by writing to
TDAR. When this register is written to (data value is not significant), the FEC RISC tells the
DMA to read the next transmit BD in the ring. After started, the RISC + DMA continues to
read and interpret transmit BDs in order and DMA the associated buffers until a transmit BD
is encountered with the R bit cleared. At this point, the FEC polls this BD one more time. If
the R bit is cleared the second time, RISC stops the transmit descriptor read process until
software sets up another transmit frame and writes to TDAR.
When the DMA of each transmit buffer is complete, the DMA writes back to the BD to clear
the R bit, indicating that the hardware consumer is finished with the buffer.
48.5.3.1.2 Driver/DMA operation with receive BDs
Unlike transmit, the length of the receive frame is unknown by the driver ahead of time.
Therefore, the driver must set a variable to define the length of all receive buffers. In the
FEC, this variable is written to the EMRBR register.
The driver (RxBD software producer) should set up some number of empty buffers for the
Ethernet by initializing the address field and the E and W bits of the associated receive BDs.
The hardware (receive DMA) consumes these buffers by filling them with data as frames are
received and clearing the E bit and writing to the L bit (1 indicates last buffer in frame), the
frame status bits (if L is set), and the length field.
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