STMicroelectronics SPC572L series Reference Manual page 1212

Deserial Serial Peripheral Interface (DSPI)
46.5.12.1 End of Queue interrupt request
The End of Queue Request indicates that the end of a transmit queue is reached. The End
of Queue Request is generated when the EOQ bit in the executing SPI command is set and
the EOQF_RE bit in the RSER is set.
When MCR[XSPI] is enabled and the EOQ bit in the executing SPI command is set, the End
of Queue Request will only be generated once the last Data frame in the Command Cycle
has been transmitted.
Note: This interrupt request is generated when the last bit of the SPI frame with EOQ bit set is
transmitted.
46.5.12.2 Transmit FIFO Fill interrupt or DMA request
The Transmit FIFO Fill Request indicates that the TX FIFO is not full. The Transmit FIFO Fill
Request is generated when the number of entries in the TX FIFO is less than the maximum
number of possible entries, and the TFFF_RE bit in the RSER is set. The TFFF_DIRS bit in
the RSER selects whether a DMA request or an interrupt request is generated.
Note: TFFF flag clears automatically when DMA is used to fill TXFIFO.
Note: To clear TFFF when not using DMA, follow these steps for every PUSH performed using
CPU to fill TXFIFO:
• Wait until TFFF = 1
• Write data to PUSHR using CPU.
• Clear TFFF by writing a '1' to its location. If TX FIFO is not full, this flag will not clear.
46.5.12.3 Command FIFO Fill interrupt or DMA request
The Command FIFO Fill Request indicates that the CMD FIFO is not full. The Command
FIFO Fill Request is generated when the number of entries in the CMD FIFO is less than the
maximum number of possible entries, and the CMDFFF_RE bit in the RSER is set. The
CMDFFF_DIRS bit in the RSER selects whether a DMA request or an interrupt request is
generated.
This Request is useful when MCR[XSPI] is enabled and hence TX FIFO and CMD FIFO can
be filled independently. If MCR[XSPI] is disabled, then 'TX FIFO Fill Interrupt or DMA
Request' will suffice to fill both FIFO's since both FIFO's must be filled simultaneously.
Note: CMDFFF flag clears automatically when DMA is used to fill CMD FIFO.
Note: To clear CMDFFF when not using DMA, follow these steps for every PUSH performed using
CPU to fill CMD FIFO:
• Wait until CMDFFF = 1
• Write data to Command field of PUSHR using CPU.
• Clear CMDFFF by writing a '1' to its location. If CMD FIFO is not full, this flag will not
clear.
46.5.12.4 Transmit FIFO Invalid Write interrupt request
The Transfer Fifo Invalid Write Request is valid only when MCR[XSPI] is enabled. This
Request indicates that Data exists in the TX FIFO while the CMD FIFO is empty. Since no
Command Fields are associated with the Data present in TX FIFO, this data is considered
1212/2058 DocID027809 Rev 4
RM0400