Texas Instruments OMAP5912 Reference Manual page 1165

MicroWire Interface
Table 39. Transmit Data Register (TDR)
Bit Name
15:0 TD
Note: MSB (bit 15) is the first transmitted bit.
Table 40. Receive Data Register (RDR)
Bit Name
15:0 RD
Note: LSB (bit 0) is the last received bit.
Table 41. Control and Status Register (CSR)
Bit Name
15 RDRB
14 CSRB
100 Serial Interfaces
Base Address = 0xFFFB 3000, Offset = 0x00
Function
Data to transmit
Whatever its size, the word is aligned on the most-significant bit (MSB) side.
Base Address = 0xFFFB 3000, Offset = 0x00
Function
Received data
Whatever its size, the word is aligned on the least-significant bit (LSB) side.
Base Address = 0xFFFB 3000, Offset = 0x04
Function
RDRB bit at 1 indicates that the receive (RDR) is
full. When the controller reads the content of the
RDR, this bit is cleared.
This bit is read only.
CSRB bit at 0 indicates that the control and status
(CSR) is ready to receive new data.
After starting a µWire transfer with the CSR, this bit
is set to 1. When the corresponding action has been
done, CSRB is reset. This bit is controlled by a
µWire internal state machine running on the F_INT
internal clock (12 MHz/N). If the CSR is read just
after being written, and the MPU is running at high
frequency (60 MHz or 120 MHz, for instance)
compared to the internal clock, the CSRB status bit
may still be low for the first read access. The CSRB
latency is 0 if the transfer was initiated by modifying
the CS_CMD bit, but it can be 0 −3 cycles if initiated
by the START bit. Suggested workarounds are a) to
have a few NOPs between initiating a µWire
transfer and checking CSRB status or, b) to check
that CSRB first has a high value on an initial read
before it goes low on a subsequent read.
This bit is read only.
Reset
Undefined
Reset
Undefined
Reset
0
0
SPRU760B