Texas Instruments OMAP5912 Reference Manual page 1177

Multimedia processor device overview and architecture
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MicroWire Interface
Figure 37.
Read Cycle in Autotransmit Mode
WIRE_NCS
UWIRE_SCCLK
UWIRE_SDO
UWIRE_SDI
112
Serial Interfaces
3) SR3 = CLK_EN: 1
CK_FREQ: 00 (must wait for 1 ARMXOR_CK + 1 F_INT cycle before any
other register access)
4) SR4 = CLK_IN: 1
5) Set the following fields of the control and status register (CSR):
NB_BITS_RD: 5
-
NB_BITS_WR: 7
-
INDEX: 00
-
CS_CMD: 0
-
START: 0
-
6) Wait for the CSRB = 0 of the control and status register (CSR).
7) Load the transmit data register (TDR) with:
A6 A5 A4 A3 A2 A1 A0 x x x x x x x x x x: Don't care
J
A6 ... A0: Address of the selected memory register
J
Transfer is automatically started.
8) Wait until CSRB = 0 and RDRB = 1 (status bits of CSR).
9) Read the content of receive data register (RDR).
10) To continue reading data external component, go to 5 else go to 11.
11) 20
12) Release autotransmit mode: SR5 = AUTO_TX_EN: 0.
13) END
The corresponding behavior of the serial interface is described in Figure 37.
A6
A5
A4
A3
A2
A1
A0
D4
D3
D2
D1
D0
SPRU760B

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