Texas Instruments OMAP5912 Reference Manual page 1166

Multimedia processor device overview and architecture
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Table 41. Control and Status Register (CSR) (Continued)
Bit
Name
13
START
12
CS_CMD
11:10
INDEX
9:5
NB_BITS_WR
4:0
NB_BITS_RD
Table 42. Setup Register 1 (SR1)
Bit
Name
11
CS1_CHK
10:9
CS1_FRQ
8
CS1CS_LVL
7
CS1_EDGE_WR
6
CS1_EDGE_RD
Content of this register must not be changed when a read or write process is running.
Note:
SPRU760B
Base Address = 0xFFFB 3000, Offset = 0x04
Function
1: Start a write and/or a read process.
This bit is automatically reset by internal logic when
a write or a read process is activated.
Send NB_BITS_WR bits (contained in TDR) to the
serial output DO. If NB_BITS_WR is equal to zero,
then the write process is not started.
Receive NB_BITS_RD bits from the serial input DI
and store them in RDR.
1: Set the chip-select of the selected device to its
active level.
Index of the external device
00: CS0
01: CS1
10: CS2
11: CS3
Number of bits to transmit
Number of bits to receive
Base Address = 0xFFFB 3000, Offset = 0x08
Function
Idem CS0_CHK.
Used when the CS1 is selected.
Defines the frequency of the serial clock SCLK
when CS1 is selected
00 : F_INT/2
01 : F_INT/4
10 : F_INT/8
11 : undefined
Defines the active level of the CS1 chip-select.
Idem CS0_EDGE_WR when CS1 is selected.
Idem CS0_EDGE_RD when CS1 is selected.
MicroWire Interface
Reset
0
0
Undefined
Undefined
Undefined
Reset
0xX (undefined)
0xX (undefined)
0x0
0xX (undefined)
0xX (undefined)
Serial Interfaces
101

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