STMicroelectronics SPC572L series Reference Manual page 1469

RM0400
Field
Reduced Over Sampling Enable
8
0 Each bit is over sampled sixteen times.
1 OSR bits decide the over sampling rate.
ROSE
The default value of this bit is 0.
Number of expected frame
9–11
These bits are used to configure the number of expected frames in UART reception mode. If the
NEF DTU bit is set, then the UART timeout counter will be reset after the configured number of frames
have been received.
Disable Timeout in UART mode
0 Timeout has to be handled by software
1 Timeout in UART mode is disabled after the configured number of data frames are received
12 This bit can be programmed in initialization mode only when the UART bit is set.
DTU_PCETX There is an internal counter that gives the number of frames received (num_of_frames).
When num_of_frames equals NEF, Disable Timeout is set and num_of_frames gets reset to
zero, restarting the timer and enabling the timeout again.
Stop bits in UART reception mode
When the UART is used for transmission and reception we have to set the same number of stop
bits in GCR and SBUR. When the UART is used only as receiver, it is enough to set SBUR bits
only.
13–14
00 1 stop bit
SBUR
01 2 stop bits
10 3 stop bits
11 Reserved
This bit can be programmed in the initialization mode only, when the UART bit is set.
Special Word Length in UART mode
0 This bit is disabled.
1 This bit enables 12-bit + parity bit in reception (UART mode) for MSC (Micro Second Channel
15
upstream frame) support.
WLS
This bit can be programmed in initialization mode only when the UART bit is set. Parity check is
enabled by default in this mode and PC0/1 bits can be used to select the parity control. This bit is
given the highest priority in UART reception mode.
Table 830. UARTCR field descriptions(Continued)
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Description
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