STMicroelectronics SPC572L series Reference Manual page 1674

e200z215An3 Core Debug Support
Bit Name
Data Address Compare 3/4 Mode
00 Exact address compare. DAC3 debug events can only occur if the address of the data
01 Address bit match. DAC3 debug events can occur only if the address of the data access
8:9 DAC34M
10 Inclusive address range compare. DAC3 debug events can occur only if the address of the
11 Exclusive address range compare. DAC3 debug events can occur only if the address of
Data Address Compare 3 Linked
0 No effect
1 DAC3 debug events are linked to IAC5 debug events. IAC5 debug events do not affect
10 DAC3LNK
When linked to IAC5, DAC3 debug events are conditioned based on whether the instruction
also generated an IAC5 debug event. Note that linking is only available in EDM or IDM.
Data Address Compare 4 Linked
0 No effect
1 DAC4 debug events are linked to IAC7 debug events. IAC7 debug events do not affect
11 DAC4LNK
When linked to IAC7, DAC4 debug events are conditioned based on whether the instruction
also generated an IAC7 debug event. Note that linking is only available in EDM or IDM.
12:31 — Reserved
57.3.2.9 Debug Status Register (DBSR)
The Debug Status Register (DBSR) contains status on debug events and the most recent
processor reset. The Debug Status Register is set via hardware, and read and cleared via
software. Bits in the Debug Status Register can be cleared using mtspr DBSR,RS. Clearing
is done by writing to the Debug Status Register with a 1 in any bit position that is to be
cleared and 0 in all other bit positions. The write data to the Debug Status Register is not
direct data, but a mask. A '1' causes the bit to be cleared, and a '0' has no effect. Debug
Status bits are set by Debug events only while Internal Debug mode is enabled
(DBCR0
IDM
EDBCR0
resource(s) via EDBRAC0), a set bit in DBSR other than MRR, DAC_OFST, or VLES will
cause a debug interrupt to be generated. The debug interrupt handler is responsible for
clearing DBSR bits prior to returning to normal execution. When resource sharing is
enabled, (EDBCR0
modified by software, and status bits associated with hardware-owned resources will not be
set by hardware in DBSR. The DBSR register is shown in
1674/2058
Table 946. DBCR8 field descriptions (Continued)
access is equal to the value specified in DAC3. DAC4 debug events can only occur if the
address of the data access is equal to the value specified in DAC4.
ANDed with the contents of DAC4, are equal to the contents of DAC3 also ANDed with the
contents of DAC4. DAC4 debug events do not occur. DAC3US and DAC3ER settings are
used.
data access is greater than or equal to the value specified in DAC3 and less than the value
specified in DAC4. DAC4 debug events do not occur. DAC3US and DAC3ER settings are
used.
the data access is less than the value specified in DAC3 or is greater than or equal to the
value specified in DAC4. DAC4 debug events do not occur. DAC3US and DAC3ER
settings are used.
DBSR
DBSR
=1). When debug interrupts are enabled (MSR
=0, or MSR =1, DBCR0
EDM DE
=1 and EDBRAC0
EDM
DocID027809 Rev 4
Description
DE
=1, EDBCR0 =1 and software is allocated
IDM EDM
=1), only software-owned resources may be
IDM
Figure
=1 DBCR0 =1 and
IDM
996.
RM0400