STMicroelectronics SPC572L series Reference Manual page 1642

Mode Entry Module (MC_ME)
56.4.5.2 Invalid Mode Transition Interrupt
The mode transition request is considered invalid under the following conditions:
•
If the system is in the
active, and if the target mode requested is other than
mode request is considered to be invalid, and the S_SEA bit of the ME_IMTS register
is set.
• If the TARGET_MODE bit field of the ME_MCTL register is written with a value
different from the specified mode values (i.e., a non-existing mode), an invalid mode
transition event is generated. When such a non existing mode is requested, the
S_NMA bit of the ME_IMTS register is set. This condition is detected regardless of
whether the proper key mechanism is followed while writing the ME_MCTL register.
•
If some of the chip modes are disabled as programmed in the ME_ME register, their
respective configurations are considered reserved, and any access to the ME_MCTL
register with those values results in an invalid mode transition request. When such a
disabled mode is requested, the S_DMA bit of the ME_IMTS register is set. This
condition is detected regardless of whether the proper key mechanism is followed while
writing the ME_MCTL register.
•
If the target mode is not a valid mode with respect to the current mode, the mode
request illegal status bit S_MRI of the ME_IMTS register is set. This condition is
detected only when the proper key mechanism is followed while writing the ME_MCTL
register. Otherwise, the write operation is ignored.
•
If further new mode requests occur while a mode transition is in progress (the
S_MTRANS bit of the ME_GS register is '1'), the mode transition illegal status bit
S_MTI of the ME_IMTS register is set. This condition is detected only when the proper
key mechanism is followed while writing the ME_MCTL register. Otherwise, the write
operation is ignored.
Note: As the causes of invalid mode transitions may overlap at the same time, the priority
implemented for invalid mode transition status bits of the ME_IMTS register in the order
from highest to lowest is S_SEA, S_NMA, S_DMA, S_MRI, and S_MTI.
As an exception, the mode transition request is not considered as invalid under the following
conditions:
•
A new request is allowed to enter the
transition status.
•
As the exit of
can occur at any instant, these requests to return to
•
In order to avoid any unwanted lockup of the chip modes, software can abort a mode
transition by requesting the parent mode if, for example, the mode transition has not
completed after a software determined 'reasonable' amount of time for whatever
reason. The parent mode is the chip mode before a valid mode request was made.
•
Self-transition requests (e.g.,
the mode transition process is active (i.e., S_MTRANS is '1'). During the low-power
mode exit process, if the system is not able to enter the respective
properly (i.e., all status bits of the ME_GS register match with configuration bits in the
ME_<mode>_MC register), then software can only request the
It is not possible to request any other mode or to go back to the low-power mode again.
Whenever an invalid mode request is detected, the interrupt pending bit I_IMODE of the
ME_IS register is set, and an interrupt request is generated if the mask bit M_IMODE of the
ME_IM register is '1'.
1642/2058
SAFE mode and the
HALT0 and STOP0 modes depends on the interrupts of the system which
RUN0
DocID027809 Rev 4
SAFE mode request from MC_RGM is
RESET
RESET or SAFE mode irrespective of the mode
RUN0...3
→ RUN0) are not considered as invalid even when
RM0400
or SAFE, then this new
modes are always valid.
RUN0...3 mode
SAFE or RESET mode.