STMicroelectronics SPC572L series Reference Manual page 1699

RM0400
To support operation of this system pin, the OnCE logic supplies the jd_de_en output and
samples the jd_de_b input when OnCE is enabled (jd_en_once asserted). Assertion of
jd_de_b will cause the OnCE logic to place the CPU into Debug mode. Once Debug mode
has been entered, the jd_de_en output will be asserted for three j_tclk periods to signal an
acknowledge. jd_de_en can be used to enable the open-drain pulldown of the system level
DE_b pin.
For systems that do not implement a system level bidirectional open drain debug event pin
DE_b, the jd_de_en and jd_de_b signals may still be used to handshake debug entry.
57.5.5.3 OnCE Debug output (jd_debug_b)
The OnCE Debug output jd_debug_b is used to indicate to on-chip resources that a debug
session is in progress. Peripherals and other units may use this signal to modify normal
operation for the duration of a debug session, which may involve the CPU executing a
sequence of instructions solely for the purpose of visibility/system control that are not part of
the normal instruction stream the CPU would have executed had it not been placed in
debug mode. This signal is asserted the first time the CPU enters the debug state, and
remains asserted until the CPU is released by a write to the OnCE Command Register with
the GO and EX bits set, and a register specified as either "No Register Selected" or the
CPUSCR. This signal will remain asserted even though the CPU may enter and exit the
debug state for each instruction executed under control of the OnCE controller. See
Section 57.5.6.2, OnCE Command (OCMD) register
the GO and EX bits. This signal is not normally used by the CPU.
57.5.5.4 CPU Clock On input (jd_mclk_on)
The CPU Clock On input jd_mclk_on is used to indicate that the CPU's m_clk input is
active. This input signal is expected to be driven by system logic external to the
e200z215An3 core, is synchronized to the j_tclk (scan clock) clock domain, and is
presented as a status flag on the j_tdo output during the Shift_IR state. External firmware
may use this signal to ensure proper scan sequences will occur to access debug resources
in the m_clk clock domain.
57.5.5.5 Watchpoint events (jd_watchpt[0:31])
The jd_watchpt[0:31] signals may be asserted by the OnCE control logic to signal that a
watchpoint condition has occurred. Watchpoints do not directly cause the CPU to be
affected. They are provided to allow external visibility only or for triggering purposes.
Watchpoint events are conditioned by the settings in the DBCRxx registers, as well as by
the DEVENT register, the DTC/DTSA/DTEA registers, and the Performance Monitor control
register settings. Refer to
assertion of most watchpoint outputs is conditioned on being in EDM or IDM. The
Performance monitor, DEVENT, and DTC watchpoints are not conditioned however, and
may assert regardless of the state of EDM or IDM. In addition, DAC1 or DAC3 watchpoints
may be generated for stack limit violation occurrences when those resources are configured
to perform stack limit checking, regardless of the state of EDM or IDM.
57.5.5.6 Update DR w/go+exit (j_ocmd_go_exit)
This signal indicates the TAP controller is in the Update_DR state and that the go and exit
bits in the OnCE Command register are high, and RS indicates "no register selected". This
signal will assert regardless of whether the CPU is currently in debug mode. It may be
monitored by external logic to cause a synchronous exit from debug mode of other modules
Table 962 for details of the signal assignments. Note that
DocID027809 Rev 4
e200z215An3 Core Debug Support
for more information on the function of
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