STMicroelectronics SPC572L series Reference Manual page 1679

RM0400
Bit Name
Data Address Compare 1 Debug Event
0 Event owned by hardware debug. No mtspr access by software to DAC1 control and status
12 DAC1
1 Event owned by software debug. DAC1 control fields are software readable/writable.
Data Address Compare 3 and 4 Debug Events
0 Events owned by hardware debug. No mtspr access by software to DAC3 and DAC4
13 DAC34
1 Event owned by software debug. DAC3 and DAC4 control fields are software
Data Address Compare 2 Debug Event
0 Event owned by hardware debug. No mtspr access by software to DAC2 control and status
14 DAC2
1 Event owned by software debug. DAC2 control fields are software readable/writable.
15 — Reserved
Return Debug Event
16 RET
0 Event owned by hardware debug. No mtspr access by software to DBCR0
1 Event owned by software debug. DBCR0
Instruction Address Compare 5 Debug Event
0 Event owned by hardware debug. No mtspr access by software to IAC5 control and status
17 IAC5
1 Event owned by software debug. IAC5 control fields are software readable/writable.
Instruction Address Compare 6 Debug Event
0 Event owned by hardware debug. No mtspr access by software to IAC6 control and status
18 IAC6
1 Event owned by software debug. IAC6 control fields are software readable/writable.
Instruction Address Compare 7 Debug Event
0 Event owned by hardware debug. No mtspr access by software to IAC7 control and status
19 IAC7
1 Event owned by software debug. IAC7 control fields are software readable/writable.
Instruction Address Compare 8 Debug Event
0 Event owned by hardware debug. No mtspr access by software to IAC8 control and status
20 IAC8
1 Event owned by software debug. IAC8 control are software readable/writable.
External Debug Event Input 1 Debug Event
21 DEVT1
0 Event owned by hardware debug. No mtspr access by software to DBCR0
1 Event owned by software debug. DBCR0
External Debug Event Input 2 Debug Event
22 DEVT2
0 Event owned by hardware debug. No mtspr access by software to DBCR0
1 Event owned by software debug. DBCR0
Performance Monitor Interrupt Debug Event
0 Event owned by hardware debug. No mtpmr access by software to the PMRs.
23 PMI
1 Event owned by software debug. PMRs are software readable/writable.
Note: This bit is reset to '1'.
24 — Reserved
Table 948. EDBRAC0 field descriptions (Continued)
fields.
control and status fields.
readable/writable.
fields.
fields.
fields.
fields.
fields.
Performance monitor interrupts set EDBSR0
DocID027809 Rev 4
e200z215An3 Core Debug Support
Description
is software readable/writable.
RET
is software readable/writable.
DEVT1
is software readable/writable.
DEVT2
regardless of the setting of PMGC0
PMI
field.
RET
field.
DEVT1
field.
DEVT2
UDI
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