STMicroelectronics SPC572L series Reference Manual page 1661

RM0400
Bit Name
Instruction Address Compare 1/2 Mode
00 Exact address compare. IAC1 debug events can only occur if the address of the instruction
01 Address bit match. IAC1 debug events can occur only if the address of the instruction fetch,
8:9 IAC12M
10 Inclusive address range compare. IAC1 debug events can occur only if the address of the
11 Exclusive address range compare. IAC1 debug events can occur only if the address of the
10:15 — Reserved
Instruction Address Compare 3 User/Supervisor Mode
00 IAC3 debug events not affected by MSR
16:17 IAC3US
01 Reserved
10 IAC3 debug events can only occur if MSR
11 IAC3 debug events can only occur if MSR
Instruction Address Compare 3 Effective/Real Mode
00 IAC3 debug events are based on effective address
18:19 IAC3ER
01 Unimplemented (Book E real address compare), no match can occur
10 IAC3 debug events are based on effective address and can only occur if MSR
11 IAC3 debug events are based on effective address and can only occur if MSR
Instruction Address Compare 4 User/Supervisor Mode
00 IAC4 debug events not affected by MSR
20:21 IAC4US
01 Reserved
10 IAC4 debug events can only occur if MSR
11 IAC4 debug events can only occur if MSR
Instruction Address Compare 4 Effective/Real Mode
00 IAC4 debug events are based on effective address
22:23 IAC4ER
01 Unimplemented (Book E real address compare), no match can occur
10 IAC4 debug events are based on effective address and can only occur if MSR
11 IAC4 debug events are based on effective address and can only occur if MSR
Instruction Address Compare 3/4 Mode
00 Exact address compare. IAC3 debug events can only occur if the address of the instruction
01 Address bit match. IAC3 debug events can occur only if the address of the instruction fetch,
24:25 IAC34M
10 Inclusive address range compare. IAC3 debug events can occur only if the address of the
11 Exclusive address range compare. IAC3 debug events can occur only if the address of the
26:31 — Reserved
Table 940. DBCR1 field descriptions (Continued)
fetch is equal to the value specified in IAC1. IAC2 debug events can only occur if the address
of the instruction fetch is equal to the value specified in IAC2.
ANDed with the contents of IAC2 are equal to the contents of IAC1, also ANDed with the
contents of IAC2. IAC2 debug events do not occur. IAC1US and IAC1ER settings are used.
instruction fetch is greater than or equal to the value specified in IAC1 and less than the value
specified in IAC2. IAC2 debug events do not occur. IAC1US and IAC1ER settings are used.
instruction fetch is less than the value specified in IAC1 or is greater than or equal to the value
specified in IAC2. IAC2 debug events do not occur. IAC1US and IAC1ER settings are used.
fetch is equal to the value specified in IAC3. IAC4 debug events can only occur if the address
of the instruction fetch is equal to the value specified in IAC4.
ANDed with the contents of IAC4 are equal to the contents of IAC3, also ANDed with the
contents of IAC4. IAC4 debug events do not occur. IAC3US and IAC3ER settings are used.
instruction fetch is greater than or equal to the value specified in IAC3 and less than the value
specified in IAC4. IAC4 debug events do not occur. IAC3US and IAC3ER settings are used.
instruction fetch is less than the value specified in IAC3 or is greater than or equal to the value
specified in IAC4. IAC4 debug events do not occur. IAC3US and IAC3ER settings are used.
Description
PR
=0 (Supervisor mode)
PR
=1 (User mode)
PR
PR
=0 (Supervisor mode).
PR
=1. (User mode)
PR
DocID027809 Rev 4
e200z215An3 Core Debug Support
=0
IS
=1
IS
=0
IS
=1
IS
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