STMicroelectronics SPC572L series Reference Manual page 1659

RM0400
Bit Name
Instruction Address Compare 3 Debug Event Enable
10 IAC3
0 IAC3 debug events are disabled
1 IAC3 debug events are enabled
Instruction Address Compare 4 Debug Event Enable
11 IAC4
0 IAC4 debug events are disabled
1 IAC4 debug events are enabled
Data Address Compare 1 Debug Event Enable
00 DAC1 debug events are disabled
12:13 DAC1
01 DAC1 debug events are enabled only for store-type data storage accesses
10 DAC1 debug events are enabled only for load-type data storage accesses
11 DAC1 debug events are enabled for load-type or store-type data storage accesses
Data Address Compare 2 Debug Event Enable
00 DAC2 debug events are disabled
14:15 DAC2
01 DAC2 debug events are enabled only for store-type data storage accesses
10 DAC2 debug events are enabled only for load-type data storage accesses
11 DAC2 debug events are enabled for load-type or store-type data storage accesses
Return Debug Event Enable
16 RET
0 RET debug events are disabled
1 RET debug events are enabled
Instruction Address Compare 5 Debug Event Enable
17 IAC5
0 IAC5 debug events are disabled
1 IAC5 debug events are enabled
Instruction Address Compare 6 Debug Event Enable
18 IAC6
0 IAC6 debug events are disabled
1 IAC6 debug events are enabled
Instruction Address Compare 7 Debug Event Enable
19 IAC7
0 IAC7 debug events are disabled
1 IAC7 debug events are enabled
Instruction Address Compare 8 Debug Event Enable
20 IAC8
0 IAC8 debug events are disabled
1 IAC8 debug events are enabled
External Debug Event 1 Enable
21 DEVT1
0 DEVT1 debug events are disabled
1 DEVT1 debug events are enabled
External Debug Event 2 Enable
22 DEVT2
0 DEVT2 debug events are disabled
1 DEVT2 debug events are enabled
23:24 — Reserved
Critical Interrupt Taken Debug Event Enable
25 CIRPT
0 CIRPT debug events are disabled
1 CIRPT debug events are enabled
Table 939. DBCR0 field descriptions (Continued)
DocID027809 Rev 4
e200z215An3 Core Debug Support
Description
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