STMicroelectronics SPC572L series Reference Manual page 1717

RM0400
Table 962. Watchpoint output signal assignments(Continued)
Signal Name
jd_watchpt[14]
jd_watchpt[15]
jd_watchpt[16]
jd_watchpt[17]
jd_watchpt[18]
jd_watchpt[19]
jd_watchpt[20]
jd_watchpt[21]
jd_watchpt[22]
jd_watchpt[23]
jd_watchpt[24]
jd_watchpt[25]
jd_watchpt[26]
jd_watchpt[27]
jd_watchpt[28]
jd_watchpt[29]
Type
Instruction Address Compare 7 watchpoint
IAC7
Asserted whenever an IAC7 compare occurs regardless of being enabled to
set DBSR status
Instruction Address Compare 8 watchpoint
IAC8
Asserted whenever an IAC8 compare occurs regardless of being enabled to
set DBSR status
Interrupt watchpoint
IRPT
Asserted whenever an IRPT debug event occurs regardless of being
enabled to set DBSR status
Return watchpoint
RET
Asserted whenever a RET debug event occurs regardless of being enabled
to set DBSR status
Critical Interrupt watchpoint
CIRPT
Asserted whenever a CIRPT debug event occurs regardless of being
enabled to set DBSR status
Critical Return watchpoint
CRET
Asserted whenever a CRET debug event occurs regardless of being
enabled to set DBSR status
Debug Event Output 2 watchpoint
DEVNT2
Asserted whenever a '1' is written to the bit of the DEVNT field of the
DEVENT debug register corresponding to jd_watchpt[20]
Debug Event Output 3 watchpoint
DEVNT3
Asserted whenever a '1' is written to the bit of the DEVNT field of the
DEVENT debug register corresponding to jd_watchpt[21]
Performance Monitor Event input watchpoint
PMEVENT
Asserted whenever p_pm_event transitions from a '0' to a '1' while m_clk is
running
Performance Monitor Counter 0 watchpoint
PMC0
Asserted whenever PMC0 triggers an event based on PMLCa0
Performance Monitor Counter 1 watchpoint
PMC1
Asserted whenever PMC1 triggers an event based on PMLCa1
Performance Monitor Counter 2 watchpoint
PMC2
Asserted whenever PMC2 triggers an event based on PMLCa2
Performance Monitor Counter 3 watchpoint
PMC3
Asserted whenever PMC3 triggers an event based on PMLCa3
— Reserved
TRAP watchpoint
TRAP
Asserted whenever an TRAP debug event occurs regardless of being
enabled to set DBSR status
Data Trace Control Range 1 watchpoint
DTC1
Asserted whenever an access meets the conditions for DTC Range 1
DocID027809 Rev 4
e200z215An3 Core Debug Support
Description
PMP
PMP
PMP
PMP
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