STMicroelectronics SPC572L series Reference Manual page 1615

RM0400
Table 927. Debug Mode Transition Status Register (ME_DMTS) field descriptions(Continued)
Field
25
CDP_PRPH_192_223
26
CDP_PRPH_160_191
27
CDP_PRPH_128_159
28
CDP_PRPH_96_127
29
CDP_PRPH_64_95
30
CDP_PRPH_32_63
31
CDP_PRPH_0_31
1. Peripheral n corresponds to the ME_PCTLn register. Please refer to
occupied, which in turn indicates which peripherals are reported in the ME_DMTS register.
Clock Disable Process Pending status for Peripherals 192...2232 — This bit is set
when any peripheral appearing in ME_PS6 has been requested to have its clock disabled.
It is cleared when all these peripherals which have been requested to have their clocks
disabled have entered the state in which their clocks may be disabled.
0 No peripheral clock disabling is pending
1 Clock disabling is pending for at least one peripheral
Clock Disable Process Pending status for Peripherals 160...191
when any peripheral appearing in ME_PS5 has been requested to have its clock disabled.
It is cleared when all these peripherals which have been requested to have their clocks
disabled have entered the state in which their clocks may be disabled.
0 No peripheral clock disabling is pending
1 Clock disabling is pending for at least one peripheral
Clock Disable Process Pending status for Peripherals 128...159
when any peripheral appearing in ME_PS4 has been requested to have its clock disabled.
It is cleared when all these peripherals which have been requested to have their clocks
disabled have entered the state in which their clocks may be disabled.
0 No peripheral clock disabling is pending
1 Clock disabling is pending for at least one peripheral
Clock Disable Process Pending status for Peripherals 96...127
any peripheral appearing in ME_PS3 has been requested to have its clock disabled. It is
cleared when all these peripherals which have been requested to have their clocks
disabled have entered the state in which their clocks may be disabled.
0 No peripheral clock disabling is pending
1 Clock disabling is pending for at least one peripheral
Clock Disable Process Pending status for Peripherals 64...95
any peripheral appearing in ME_PS2 has been requested to have its clock disabled. It is
cleared when all these peripherals which have been requested to have their clocks
disabled have entered the state in which their clocks may be disabled.
0 No peripheral clock disabling is pending
1 Clock disabling is pending for at least one peripheral
Clock Disable Process Pending status for Peripherals 32...63
any peripheral appearing in ME_PS1 has been requested to have its clock disabled. It is
cleared when all these peripherals which have been requested to have their clocks
disabled have entered the state in which their clocks may be disabled.
0 No peripheral clock disabling is pending
1 Clock disabling is pending for at least one peripheral
Clock Disable Process Pending status for Peripherals 0...31
any peripheral appearing in ME_PS0 has been requested to have its clock disabled. It is
cleared when all these peripherals which have been requested to have their clocks
disabled have entered the state in which their clocks may be disabled.
0 No peripheral clock disabling is pending
1 Clock disabling is pending for at least one peripheral
DocID027809 Rev 4
Mode Entry Module (MC_ME)
Description
Table 920 for the ME_PCTLn locations actually
2
— This bit is set
2
— This bit is set
2
— This bit is set when
2
— This bit is set when
2
— This bit is set when
2
— This bit is set when
1615/2058
1644