STMicroelectronics SPC572L series Reference Manual page 1637

RM0400
56.4.3.9 Pad Outputs-On
On completion of the step, if the PDO bit of the ME_<target mode>_MC register is cleared,
then
•
all pad outputs are enabled to return to their previous state
•
the slew rate control mechanism is switched on
56.4.3.10 Peripheral Clocks Enable
Based on the current and target chip modes, the peripheral configuration registers
ME_RUN_PC0...7, ME_LP_PC0...7, and the peripheral control registers ME_PCTLn, the
MC_ME enables the clocks for selected modules as required. This step is executed only
after the process is completed, and if the value of the PWRLVL field of the
ME_<target mode>_MC register is process is completed.
56.4.3.11 System and Processor Clocks Enable
On completion of the
system clock and the clocks of all processors which are configured in the ME_CCTLn
registers to be disabled in the current mode and to be running in the target mode.
The MC_ME initiates the resetting of all processors which are configured in the ME_CCTLn
registers to be running in the target mode and which have their RMC bits in the
ME_CADDRn registers set to '1'. The core_rst_b outputs remain asserted until the end of
the mode transition as indicated by the S_MTRANS bit of the MW_GS register at which time
they are deasserted.
If the value of the PWRLVL field of the ME_<target mode>_MC register is different from
that of the ME_<current mode>_MC register's, the mode change handshake will not be
initiated until after the system clock frequency ramp-down step of the
Switching
56.4.3.12 Processor Low-Power Mode Exit
On completion of the
processors which are configured in the ME_CCTLn registers to be disabled in the current
mode and to be running in the target mode.
56.4.3.13 System Clock Switching
Based on the SYSCLK bit field of the ME_<current mode>_MC and
ME_<target mode>_MC registers, if the target and current system clock configurations
differ, the following method is implemented for clock switching.
•
The target clock configuration for the 16 MHz internal RC oscillator takes effect only
after the S_IRC bit of the ME_GS register is set by hardware (i.e., the 16 MHz internal
RC oscillator has stabilized).
•
The target clock configuration for the external crystal oscillator takes effect only after
the S_XOSC bit of the ME_GS register is set by hardware (i.e., the external crystal
oscillator has stabilized).
•
The target clock configuration for the PLL0 PHI takes effect only after the S_PLL0 bit of
the ME_GS register is set by hardware (i.e., the primary PLL has stabilized).
•
To disable the clock, the SYSCLK bit field should be programmed with "1111". This is
only possible in
Flash Module Switch-On
process is completed.
System and Processor Clocks Enable
TEST mode.
DocID027809 Rev 4
Mode Entry Module (MC_ME)
step, the MC_ME enables the non-processor
step, the MC_ME requests all
System Clock
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