STMicroelectronics SPC572L series Reference Manual page 1712

e200z215An3 Core Debug Support
Bit Name
PC Offset Field
This field indicates whether the value in the PC portion of the CPUSCR must be adjusted
prior to exiting debug mode. Due to the pipelined nature of the CPU, the PC value must be
backed up by emulation software in certain circumstances. The PCOFST field specifies the
value to be subtracted from the original value of the PC. This adjusted PC value should be
restored into the PC portion of the CPUSCR just prior to exiting debug mode with a go+exit.
In the event the PCOFST is non-zero, the IR should be loaded with a nop instruction instead
of the original IR value, other wise the original value of IR should be restored. (But see
16:19 PCOFST
PCINV, which overrides this field).
0000 No correction required.
0001 Subtract 0x04 from PC.
0010 Subtract 0x08 from PC.
0011 Subtract 0x0C from PC.
0100 Subtract 0x10 from PC.
0101 Subtract 0x14 from PC.
All other encodings are reserved
PC and IR Invalid Status Bit
This status bit indicates that the values in the IR and PC portions of the CPUSCR are invalid.
Exiting debug mode with the saved values in the PC and IR will have unpredictable results.
20 PCINV Debug firmware should initialize the PC and IR values in the CPUSCR with desired values
prior to exiting debug mode if this bit was set when debug mode was initially entered.
0 No error condition exists.
1 Error condition exists. PC and IR are corrupted.
Feed Forward RA Operand Bit
This control bit causes the content of the WBBRlo to be used as the RA operand value (RS
for logical, mtspr, mtdcr, cntlzw, and shift operations, RX for VLE se_ instructions, RT for
e_{logical_op}2i type instructions, RB for evaddiw, evsubifw, and the value to use as the PC
for calculating the LR update value for branch with link type instructions) of the first
instruction to be executed following an update of the CPUSCR.For most LSP instructions
using rA||rB as a 64-bit source operand, WBBRhi, lo is used to supply the 64-bit source
value.
21 FFRA
This allows the debug firmware to update processor registers — initialize the WBBRlo with
the desired value, set the FFRA bit, and execute a ori Rx,Rx,0 instruction to the desired
register.
Note: not all instructions support using the FFRA control. FFRA is mainly intended for use
with the ori instruction to allow the debugger to write to a GPR. Support for other instructions
is implementation-dependent.
0 No action.
1 Content of WBBR
IR Status Bit 0
This control bit indicates a TEA status for the IR.
22 IRSTAT0
0 No TEA occurred on the fetch of this instruction.
1 TEA occurred on the fetch of this instruction.
IR Status Bit 1
23 IRSTAT1
This control bit is reserved.
1712/2058
Table 961. CTL field descriptions (Continued)
used as operand value.
lo
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Description
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