STMicroelectronics SPC572L series Reference Manual page 1639

RM0400
down and updates its availability status bit S_<clock source> of the ME_GS register to '0'.
The following clock sources switched off at this step:
•
the 16 MHz internal RC oscillator
•
the external crystal oscillator
•
the primary PLL
For the clock sources related to the sytem clock, this step is executed only after the
Clock Switching
56.4.3.16 Flash Switch-Off
Based on the FLAON bit field of the ME_<current mode>_MC and
ME_<target mode>_MC registers, if the flash is to be put in its low-power or power-down
mode, the MC_ME requests the flash to enter the corresponding power mode and waits for
the flash to acknowledge. The exact power mode status of the flash is updated in the
S_FLA bit field of the ME_GS register. This step is executed only when the
Clocks Disable
56.4.3.17 Current Mode Update
The current mode status bit field S_CURRENT_MODE of the ME_GS register is updated
with the target mode bit field TARGET_MODE of the ME_MCTL register when :
•
all the updated status bits in the ME_GS register match the configuration specified in
the ME_<target mode>_MC register
•
power sequences are done
•
clock disable/enable process is finished
•
processor low-power mode (stop) entry and exit processes are finished
Note: SAFE mode entry does not wait for the clock disable/enable process to finish. It only waits
for the ME_GS.S_RC bit to be set. This is to ensure that the
quickly as possible.
Software can monitor the mode transition status by reading the S_MTRANS bit of the
ME_GS register. The mode transition latency can differ from one mode to another
depending on the resources' availability before the new mode request and the target mode's
requirements.
If a mode transition is taking longer to complete than is expected, the ME_DMTS register
can indicate which process is still in progress.
process has completed.
and System Clock Disable
DocID027809 Rev 4
Mode Entry Module (MC_ME)
processes have completed.
SAFE
System
Processor
mode is entered as
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