STMicroelectronics SPC572L series Reference Manual page 1719

RM0400
To return the CPU to normal operation (without disabling external debug mode)
•
The OCR
•
The debugger restores the CPUSCR with a previously saved value of the CPUSCR
(with appropriate modification of the PC and IR as described in
Control State Register
•
The OCR
To exit External Debug mode
•
The debugger should place the CPU in the debug state via the OCR
asserted, scanning out and saving the CPUSCR.
•
The debugger should write the DBCR0–8 registers as needed, likely clearing every
enable except the EDBCR0
•
The debugger should write the DBSR to a cleared state.
•
The debugger should rewrite the DBCR0 with all bits including EDM cleared.
•
The debugger should clear the OCR
•
The debugger restores the CPUSCR with the previously saved value of the CPUSCR
(with appropriate modification of the PC and IR as described in
Control State Register
•
The OCR
Note: These steps are meant by way of examples, and are not meant to be an exact template for
debugger operation.
control bit should be cleared, leaving the OCR
DR
(CTL)), with a Go+Exit OnCE Command value.
bit may then be cleared.
WKUP
EDM
(CTL)), with a Go+Exit OnCE Command value.
bit may then be cleared.
WKUP
DocID027809 Rev 4
e200z215An3 Core Debug Support
bit.
bit.
DR
bit set.
WKUP
Section 57.5.9.2,
with OCR
DR
Section 57.5.9.2,
1719/2058
WKUP
1719