STMicroelectronics SPC572L series Reference Manual page 1687

RM0400
by hardware, then a normal DAC event is generated (but qualified with use of GPR R1), and
debug mode entry will occur in the same manner as for a non-stack limit DAC event.
Enabling of this functionality is described in more detail in
required to be set for software-owned stack limit checking.
In contrast to the normal case of DAC address matching resulting in a debug event, the
stack limit check address compare logic operates differently for stack limit checking. When
using resources for stack limit checking, a DACn hit to a resource enabled for performing
stack limit checking on a stack access indicates a stack limit violation.
When stack limit checking is enabled by the setting of the DBCR4
the DBCR8
owned by software, DACn events are not generated and the DBSR DAC status flag will not
be set due to a detected stack limit hit. Instead, if stack limit checking is enabled for
supervisor mode stack accesses in DAC1 or DAC3, and a compare hit occurs for a
supervisor mode stack access (A load or store using GPR R1 in the <EA> calculation), a
machine check exception is signaled. If stack limit checking is enabled for user mode
accesses, a DSI exception is signaled when a stack limit checking enabled DAC1 or DAC3
compare hit occurs for a user mode access. A watchpoint for DAC1 or DAC3 will be
generated when the stack limit violation is detected, even though the instruction does not
complete. Stack limit checking for supervisor mode stack accesses is considered enabled
when either the DBCR4
or the DBCR7
Stack limit checking for user mode stack accesses is considered enabled when either the
DBCR4
DAC1CFG
DBCR7
DAC3CFG
unlike regular debug DAC events, both halves of a misaligned access are checked for limit
violations.
When stack limit checking is enabled for a stack access, and DACn resources are owned by
hardware, the EDBSR0 DAC status flag will be set due to a detected stack limit violation, to
cause entry into debug halted mode or to generate a watchpoint, or both, in the same way
as a DAC event normally does, i.e. after the access has completed. The only difference is
that qualification of the access address is performed as discussed in the next paragraph. If
the access is aborted due to a DSI or other exception such as machine check condition, the
EDBSR0
completed.
Stack limit checking is implemented in the same way as address compares using DACn, but
qualify a load or store access address with the use of GPR R1 as the base or index register
used to compute an effective address when a load or store instruction is executed. No stack
limit checking is performed for instructions that indicate GPR R1 is used to hold a decoration
value (for decorated load/store type instructions). When DACn resources are not owned by
hardware, if a stack limit violation occurs (a hit to a stack limit enabled DAC is detected)
when performing the load or store, the access request is aborted and the access is not
performed. Instead, for supervisor mode accesses, an error report machine check exception
is generated, with MCSRR0 pointing to the address of the load or store instruction that
generated the stack overflow/underflow, and for user mode accesses, a DSI exception is
generated, with SRR0 pointing to the address of the load or store instruction that generated
the stack overflow/underflow. If all stack limit check enabled DACn resources are owned by
hardware, then a DAC event is generated (but qualified with use of GPR R1), and debug
mode entry will occur in the same manner as for a non-stack limit DAC event. In this case,
the instruction and access will normally have completed, in the same manner as a normal
DAC event.
field to '1000' (or both), and the corresponding DACn resources are
DAC3CFG
DAC1CFG
field is set to '1000' with DBCR8
DAC3CFG
field is set to '1000' with DBCR2
field is set to '1000' with DBCR8
status bit will also be set to indicate that the data access instruction was not
IDE
DocID027809 Rev 4
field is set to '1000' with DBCR2
DAC1US
DAC3US
e200z215An3 Core Debug Support
Table 942. Note that IDM is not
field to '1000' or
DAC1CFG
set to '00' or '10',
DAC1US
set to '00' or '10', or both.
DAC3US
set to '00' or '01', or the
set to '00' or '01', or both. Note that
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