STMicroelectronics SPC572L series Reference Manual page 1714

e200z215An3 Core Debug Support
the PC value must be backed up by emulation software in certain circumstances. The
PCOFST field specifies the value to be subtracted from the original value of the PC. This
adjusted PC value should be restored in to the PC portion of the CPUSCR just prior to
exiting debug mode with a go+exit. In the event the PCOFST is non-zero, the IR should be
loaded with a nop instruction (such as ori r0,r0,0) instead of the original IR value, otherwise
the original value of IR should be restored. Note that when a correction is made to the PC
value, it will generally point to the last completed instruction, although that instruction will not
be re-executed. The nop instruction is executed instead, and instruction fetch and execution
will resume at location PC + 4. IRStat8 will be used to determine the type of instruction
present in the IR, thus should be cleared in this case. Note that debug events that may
occur on the nop (ICMP) will be generated if enabled.
For the CTL register, the internal state bits should be restored to their original value. The
IRStatus bits should be set to '0's if the PC was adjusted. If no PC adjustment was
performed, emulation firmware should determine whether other IRStat flags should be set to
'0' to avoid re-entry into debug mode for an instruction breakpoint request. Upon exiting
debug mode with go+exit, if one of these bits is set, debug mode will be reentered prior to
any further instruction execution.
57.5.9.3 Program Counter (PC) register
The PC is a 32-bit register that stores the value of the program counter that was present
when the chip entered the debug mode. It is affected by the operations performed during the
debug mode and must be restored by the external command controller when the CPU
returns to normal mode. PC normally points to the instruction contained in the IR portion of
CPUSCR. If debug firmware wishes to redirect program flow to an arbitrary location, the PC
and IR should be initialized to correspond to the first instruction to be executed upon
resumption of normal processing. Alternatively, the IR may be set to a nop and the PC set to
point to the location prior to the location at which it is desired to redirect flow to. On exiting
debug mode, the nop will be executed, and instruction fetch and execution will resume at
PC+4.
57.5.9.4 Write-Back Bus Register (WBBR
WBBR is used as a means of passing operand information between the CPU and the
external command controller. Whenever the external command controller needs to read the
contents of a register or memory location, it will force the chip to execute an instruction that
brings that information to WBBR. WBBR
including load data returned for a load or load with update instruction. WBBR
updated effective address calculated by a load with update instruction. It is undefined for
other instructions.
As an example, to read the 32 bits of processor register r1, an ori r1,r1,0 instruction is
executed, and the result value of the instruction will be latched into WBBR
of WBBR
processor resource, this register is initialized with a data value to be written, and an ori
instruction is executed, which uses this value as a substitute data value. The Control State
register FFRA bit forces the value of the WBBR
source value of the ori instruction, thus allowing updates to processor registers to be
performed. (Refer to
CTL
FFRA
WBBR
low
result, and due to control issues are not defined on lmw or branch instructions as well.
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can then be delivered serially to the external command controller. To update a
low
Section 57.5.9.2, Control State Register (CTL)
bit.)
and WBBR are generally undefined on instructions that do not writeback a
high
DocID027809 Rev 4
, WBBR )
low high
holds the 32-bit result of most instructions
low
to be substituted for the normal RS
low
RM0400
holds the
high
. The contents
low
for more detail on the