STMicroelectronics SPC572L series Reference Manual page 1538

Reset Generation Module (MC_RGM)
51.4.1.1 PHASE0 phase
This phase is entered immediately from any phase on a power-on or enabled 'destructive'
reset event. The reset state machine exits PHASE0 and enters PHASE1 on verification of
the following:
•
all enabled 'destructive' resets have been processed
•
all processes that need to be done in PHASE0 are completed PMC and 16 MHz
internal RC oscillator stabilization
•
a minimum of 8 16 MHz internal RC oscillator clock cycles have elapsed since power-
up completion and the last enabled 'destructive' reset event
•
the 'destructive' reset escalator counter has not reached the value in the DRET field of
the RGM_DRET resister
51.4.1.2 PHASE1 phase
This phase is entered either on exit from PHASE0 or immediately from PHASE2, PHASE3,
or IDLE on a non-masked external or 'functional' reset event if it has not been configured to
trigger a 'short' sequence. The reset state machine exits PHASE1 and enters PHASE2 on
verification of the following:
•
all enabled, non-shortened 'functional' resets have been processed
•
a minimum of 750 16 MHz internal RC oscillator clock cycles have elapsed since the
last enabled external or non-shortened 'functional' reset event
51.4.1.3 PHASE2 phase
This phase is entered on exit from PHASE1. The reset state machine exits PHASE2 and
enters PHASE3 on verification of the following:
•
all processes that need to be done in PHASE2 have completed flash initialization
•
a minimum of 8 16 MHz internal RC oscillator clock cycles have elapsed since entering
PHASE2
51.4.1.4 PHASE3 phase
This phase is entered either on exit from PHASE2 or immediately from IDLE on an enabled,
shortened 'functional' reset event. The reset state machine exits PHASE3 and enters IDLE
on verification of the following:
•
all processes that need to be done in PHASE3 are completed trimming and start-up
self test configuration
•
a minimum of 160 16 MHz internal RC oscillator clock cycles have elapsed since the
last enabled, shortened 'functional' reset event
•
ESR0 is not asserted, except if a start-up self test is to be executed on exit of the
current reset sequence or the EROEC bit of the RGM_EROEC register is '1'
•
PORST is not asserted, except if a start-up self test is to be executed on exit of the
current reset sequence
51.4.1.5 IDLE phase
This is the final phase and is entered on exit from PHASE3. When this phase is reached, the
MC_RGM releases control of the system to the platform and waits for new reset events that
can trigger a reset sequence.
1538/2058 DocID027809 Rev 4
RM0400