STMicroelectronics SPC572L series Reference Manual page 1614

Mode Entry Module (MC_ME)
Table 927. Debug Mode Transition Status Register (ME_DMTS) field descriptions(Continued)
Field
15
SMR
16
Reserved
17
VREG_CSRC_SC
18
CSRC_CSRC_SC
19
IRC_SC
20
SCSRC_SC
21
SYSCLK_SW
22
Reserved
23
FLASH_SC
24
CDP_PRPH_224_255
1614/2058
SAFE mode request from MC_RGM is active indicator — This bit is set if a hardware
SAFE mode request has been triggered. It is cleared when the hardware
request has been cleared.
0 A SAFE mode request is not active
1 A SAFE mode request is active
Main VREG dependent Clock Source State Change during mode transition indicator
— This bit is set when a clock source which depends on the main voltage regulator to be
powered-up is requested to change its power up/down state. It is cleared when the clock
source has completed its state change.
0 No state change is taking place
1 A state change is taking place
(Other) Clock Source dependent Clock Source State Change during mode transition
indicator — This bit is set when a clock source which depends on another clock source
to be powered-up is requested to change its power up/down state. It is cleared when the
clock source has completed its state change.
0 No state change is taking place
1 A state change is taking place
IRC State Change during mode transition indicator — This bit is set when the 16 MHz
internal RC oscillator is requested to change its power up/down state. It is cleared when
the 16 MHz internal RC oscillator has completed its state change.
0 No state change is taking place
1 A state change is taking place
Secondary Clock Sources State Change during mode transition indicator — This bit
is set when a secondary clock source is requested to change its power up/down state. It
is cleared when all secondary system clock sources have completed their state changes.
(A 'secondary clock source' is a clock source other than IRC.)
0 No state change is taking place
1 A state change is taking place
System Clock Switching pending status —
0 No system clock source switching is pending
1 A system clock source switching is pending
FLASH State Change during mode transition indicator — This bit is set when the
FLASH is requested to change its power up/down state. It is cleared when the DFLASH
has completed its state change.
0 No state change is taking place
1 A state change is taking place
Clock Disable Process Pending status for Peripherals 224...255
when any peripheral has been requested to have its clock disabled. It is cleared when all
the peripherals which have been requested to have their clocks disabled have entered
the state in which their clocks may be disabled.
0 No peripheral clock disabling is pending
1 Clock disabling is pending for at least one peripheral
DocID027809 Rev 4
Description
RM0400
SAFE mode
(1)
— This bit is set