STMicroelectronics SPC572L series Reference Manual page 1764

IEEE 1149.7 Compact JTAG Test Access Port Controller (CJTAG)
new SP payload. The DLYC register should be programmed before the use of the Advanced
Protocol begins after the use of the Standard Protocol.
Set using the STMC command.
Read using SCNS, RDBACK0
Bits 18-17 of the "Global Register."
60.6.2.3.7 Ready Control (RDYC[1:0])
The Ready Control register defines behavior exhibited in the SP payload output bit frames
when the STL stall opportunities (RDY bits) are included as control information. This register
defines the number of additional bits inserted in these bit frames. These bits provide more
time for a high-performance external tool to ascertain whether the TAP.7 controller is ready
to complete the SP payload. The use of these bits makes a high-performance external tool
design easier as input and output buffer delays play less of a role in limiting the TAP.7
controller performance. The RDYC register should be programmed before the use of the
Advanced Protocol begins.
Set using the STMC command.
Read using SCNS, RDBACK0.
Bits 18-17 of the Global register state.
60.6.2.3.8 Test Reset (TRESET)
Asserts a test reset to the STL.
•
0 – The nSYS_TRST and SYS_TMS signals presented to the STL is not influenced by
this bit.
•
1 – The nSYS_TRST presented to the STL is asserted and the SYS_TMS signal is a
logic 1.
Set using the STC1 command.
The effects of the TRESET Register may be modified by a private TAP.7 controller register.
When this private register is unimplemented or has a value of zero, the TRESET register
causes the maximum initialization of the STL with nSYS_TRST and the SYS_TMS logic 1
value. Otherwise, the value of the private register may modify the function of the TRESET
Register bit.
When the TRESET Register is a logic 1, the STL scan path appears broken as the state of
CLTAPC remains Test-Logic-Reset while the EPUTAPC state progression continues. When
the operation of the EPUTAPC and CLTAPC controllers is coupled, as with a T1 TAP.7, the
state of these two TAPCs may be resynchronized to the Run-Test/Idle state by:
•
An STC1 Command that sets the TRESET Register value to a logic 0.
•
A stay in the Run-Test/Idle state of two or more SYS_TCK periods immediately
following the Update-DR state of this command
A failure to follow the guidelines is considered a programming error and will result in
erroneous system operation. The EPUTAPC and CLTAPC states will not be synchronized
as they progress through the state diagram.
1764/2058 DocID027809 Rev 4
RM0400