STMicroelectronics SPC572L series Reference Manual page 1809

RM0400
Table 1007. JTAGM_MCR register field descriptions(Continued)
Field
7
EVTI1_ASSERT
8–17
18–23
INTER_JTAG_
FRAME_TIMER
24
25
SIE
26
IIE
27–29
TCKSEL
30
JTAGM_JCOMP
31
DTM
62.4.1.2 Status register (JTAGM_SR)
The functionality of some of the SR bits changes depending on the setting of the DTM bit in
the MCR. These differences are described in the field descriptions table.
EVTI1 Assert.
0 Asserted the EVTO1 from the JTAGM module
1 Deasserts the EVTO1 from the JTAGM module
Note: In the SW mode (when DTM =1), regardless of the state of "EVTI1_ASSERT" bit
the internall "evti" signal remains de-asserted . Though this bit can be written , yet
writing to this bit has no effect.
Reserved
TCK delay.
0000000 TCK delay
0000011 TCK delay
...
11111163 TCK delay
Reserved
SPU Interrupt Enable.
0 JTAGM does not generate an interrupt to the CPU
1 JTAGM generates an interrupt to the CPU if the SPU interrupt request is asserted
Idle Interrupt Enable.
0 JTAGM does not generate an interrupt to the CPU upon completion of a 60-bit JTAG
transfer
1 JTAGM generates an interrupt to the CPU upon completion of a 60-bit JTAG transfer
TCK Divider division factor control value. (TCK Divider divides the clock input to JTAGM
IP to generate TCK out(input to DCI)).
000 TCK Divider division factor is 1
001 TCK Divider division factor is 2
010 TCK Divider division factor is 3
...
111 TCK Divider division factor is 8
Note: It should be taken care that the maximum frequency of TCK input to DCI, should
be equal or less than half of system clock.
JTAG reset.
0 JCOMP low/asserted
1 JCOMP high/not asserted (default)
Data Transer Mode
1 Data for JTAG transferred by software.
0 Data transferred by software disabled.
DocID027809 Rev 4
Description
JTAG Master (JTAGM)
1809/2058
1814