Low-Power Sleep Mode (Lpsleep); Table 49. Sleep Mode - STMicroelectronics STM32WL5 Series Reference Manual

RM0453
Sleep mode
Mode entry
Mode exit
Wake-up latency
6.5.6

Low-power sleep mode (LPSleep)

Refer to the product datasheet for more details on voltage regulator and peripherals
operating conditions.
I/O states in LPSleep mode
In LPSleep mode, all I/O pins keep the same state as in Run mode.
Enter LPSleep mode
The LPSleep mode is entered from LPRun mode as described in
power mode, when the SLEEPDEEP bit in the Cortex system control register is clear.
Refer to
Exit LPSleep mode
The LPSleep mode is exited as described in
exiting the LPSleep mode by issuing an interrupt or an event, the MCU is in LPRun mode.
WFI (wait for interrupt) or WFE (wait for event) while:
– SLEEPDEEP = 0
– No interrupt (for WFI) or event (for WFE) is pending
Refer to the Cortex system control register.
On return from ISR while:
– SLEEPDEEP = 0 and
– SLEEPONEXIT = 1
– No interrupt is pending
Refer to the Cortex system control register.
If WFI or return from ISR was used for entry
Interrupt: refer to
table
If WFE was used for entry and SEVONPEND = 0:
Wake-up event: refer to
If WFE was used for entry and SEVONPEND = 1:
Interrupt even when disabled in NVIC: refer to
and Table 90: CPU2 vector table
up interrupts
None
Table 50 for details on how to enter the LPSleep mode.

Table 49. Sleep mode

Description
Table 89: CPU1 vector
Table 93: Wake-up interrupts
or wake-up event: refer to
Section 6.5.4: Exit low-power
RM0453 Rev 5
Power control (PWR)
table, and Table 90: CPU2 vector
Table 89: CPU1 vector
Table 93: Wake-
Section 6.5.3: Enter low-
mode. When
table,
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