STMicroelectronics SPC572L series Reference Manual page 1906

Nexus Aurora Router (NAR)
–
–
–
–
–
•
Endianess Support
–
•
Pipeline Support
–
65.5.14.1 Operation
The trace memory bus controller allows all read/write operations to be cut through. The
controller has a pipeline depth of two. While the data phase of one transaction is ongoing, it
can accept one more read/write request from the internal bus master and initiate the
address phase on the AHB interface during the last data cycle of the ongoing transaction.
65.5.14.2 Write operation
When the trace memory bus initiator asserts a request for a write operation, it can find the
acknowledge signal parked asserted if the controller is ready to accept the transaction. If the
pipeline is full or in case of an ongoing read transaction, the controller inserts wait states by
keeping the acknowledge low. The trace memory bus controller initiates the address phase
on AHB interface once it accepts the transaction by asserting the acknowledge on the trace
memory bus interface. The write data from the trace memory bus initiator is accepted by the
gasket by asserting the acknowledge only on completion of address phase at AHB
interface, which is signified by receiving the ready signal asserted. Simultaneously, the data
is sent to the data bus. Once the requisite number of bytes have been accepted from the
trace memory bus initiator, the gasket generates end of data and transfer according to the
Trace memory bus protocol.
The AHB protocol supports data transactions of byte, half-word, word and double-word
(when both trace memory bus and AHB data bus width is 64 bits). A write transaction from
the trace memory bus initiator take place as single/multiple transactions on the AHB side.
65.5.14.3 Read operation
When the trace memory bus initiator asserts a request signal to request for a read
operation, it can find the acknowledge signal parked asserted if the gasket is ready to
accept the transaction. If the pipeline is full, the controller inserts wait states by keeping the
acknowledge low. The trace memory bus controller initiates the address phase on AHB-EW
interface once it accepts the transaction by asserting the acknowledge on trace memory bus
interface. The controller reads the data from the bus when the ready signal is sensed
asserted. The data is transferred on the trace memory bus data bus with the data
acknowledge asserted. The gasket asserts end of data and transfer at the end of
transaction as per trace memory bus protocol.
The AHB protocol supports data transactions of byte, word, half-word and double-word
(when both trace memory bus and AHB data bus width is 64-bits). A read transaction from
trace memory bus initiator takes place as single/multiple transaction on the AHB interface
before the read data is merged and sent on the trace memory bus read data bus.
1906/2058
Transfer Size
Byte, Half Word, Word, Double-Word
Protection Control
Cacheable/ Non Cacheable Access Control
User/Privilege Access
Configurable Little Endian/Big Endian support on AMBA-AHB interface
Total of two transactions (One plus one ongoing)
DocID027809 Rev 4
RM0400