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17.2 Operating Modes
The CAN module has the following four operating modes.
• CAN Reset/Initialization Mode
• CAN Operating Mode
• CAN Sleep Mode
• CAN Interface Sleep Mode
Figure 17.17 shows transition between operating modes.
MCU Reset
CAN interface
sleep mode
CCLK3: Bit in the CCLKR register
Reset, Sleep, RetBusOff: Bits in the C0CTLR register
State_Reset, tate_BusOff: Bits in the C0STR register
Figure 17.17 Transition Between Operating Modes
17.2.1 CAN Reset/Initialization Mode
The CAN reset/initialization mode is activated upon MCU reset or by setting the Reset bit in the C0CTLR
register to 1. If the Reset bit is set to 1, check that the State_Reset bit in the C0STR register is set to 1.
Entering the CAN reset/initialization mode initiates the following functions by the module:
• CAN communication is impossible.
• When the CAN reset/initialization mode is activated during an ongoing transmission in operation
mode, the module suspends the mode transition until completion of the transmission (successful,
arbitration loss, or error detection). Then, the State_Reset bit is set to 1, and the CAN reset/
initialization mode is activated.
• Registers C0MCTLj (j = 0 to 15), C0STR, C0ICR, C0IDR, C0RECR, C0TECR, and C0TSR are
initialized. All these registers are locked to prevent CPU modification.
• Registers C0CTLR, C0CONR, C0GMR, C0LMAR, and C0LMBR and the CAN0 message box
retain their contents and are available for CPU access.
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CAN reset/initialization
mode
State_Reset = 1
Sleep = 0
CCLK3 = 1
CAN sleep mode
CCLK3 = 0
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Reset = 0
Reset = 1
Sleep = 1
Reset = 1
CAN operating mode
State_Reset = 0
when 11 consecutive
recessive bits are
detected 128 times
TEC > 255
or
RetBusOff = 1
Bus off state
State_BusOff = 1
17. CAN Module
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