Texas Instruments OMAP5910 Manuals

Manuals and User Guides for Texas Instruments OMAP5910. We have 4 Texas Instruments OMAP5910 manuals available for free PDF download: Technical Reference Manual, Reference Manual

Texas Instruments OMAP5910 Technical Reference Manual (1209 pages)

Dual-Core

Brand: Texas Instruments | Category: Processor | Size: 5.5 MB

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3
Table of Contents
7
Introduction
42
Configuration Registers
44
- Description
  45
OMAP5910 Master Block Diagram
44
OMAP5910 Diagram
46
- Features
  47
- Architecture
  49
- Memory Maps
  50
DSP Memory Map
51
- Software Compatibility
  52
2 MPU Subsystem

53
3 DSP Subsystem

131
- Highlight of DSP Subsystem
  132
  - Architecture Overview
    132
- DSP Subsystem and Modules
  133
- DSP Core and Internal Bus Designations
  135
  - Tms320C55X DSP CPU Overview
    136
    
    Hardware Acceleration Modules
    137
- C55X DSP Architecture
  138
- DSP Memory
  139
- DSP Memory Connections
  140
  - Internal Memory
    140
  - Instruction Cache
    141
- DSP I-Cache Input/Output Memory-Mapped Control Registers
  142
  - System Memory
    142
- DSP Memory Space
  143
  - Peripheral Register Addresses
    144
- DSP Peripheral Mapping
  145
- DMA Controller
  146
- DMA and Ports
  147
- Possible DMA Transfers
  148
- Example of DMA Configuration
  149
- Read/Write Synchronization
  150
- DMA Controller Configuration Registers
  151
- DSP DMA Mapping
  156
  - TIPB Bridge
    157
- DSP Subsystem Modules
  158
- Control Mode Register (CMR) - Value at Reset Is 0Xfe4D
  159
- Wait States
  160
  - Idle Control and Idle Status Registers (ICR and ISTR)
    161
- Idle Configuration Register (ICR)
  162
- Idle Status Register (ISTR)
  162
  - MPU Interface
    163
    
    HOM/SAM Change Outside of Reset
    164
    
    ST3—HOM_R Bit (Bit 9)
    165
- EMIF Global Control Register (EMIF GCR)
  166
- DSP Boot Configuration
  170
  - DSP/MPU Shared Peripherals
    170
- Boot Modes
  171
- External Memory Boot Table for 16-Bit Boot Download
  172
- External Memory Boot Table for 32-Bit Boot Download
  173
4 Memory Interface Traffic Controller

175
5 System DMA Controller

234
7 MPU Public Peripherals

363
- MPU Public Peripherals Area
  364
- Camera Interface
  365
- Camera Interface Block Diagram
  366
- Image Data Transfer
  367
- Timing Chart of Image Data Transfer (POLCLK = 1)
  368
- Order of Camera Data on TIPB (Not Swapped)
  369
- Order of Camera Data on TIPB (Swapped)
  369
- FIFO Buffer Parts
  371
- Clock Ratios
  371
- IRQ Generated on VSYNC Falling Edge
  372
- Default Configuration at Reset
  373
- Camera Interface Registers
  374
- Clock Control Register (CTRLCLOCK)
  374
- Interrupt Source Status Register (IT_STATUS)
  375
- Camera Interface Mode Configuration Register (MODE)
  376
- Camera Interface GPIO Register (GPIO)
  377
- Status Register (STATUS)
  377
- Image Data Register (CAMDATA)
  378
  - Clock Switching Procedures
    378
  - MPU I/O Interrupts
    379
- Keyboard Scanning Sequence
  381
  - MPUIO Keyboard Interface
    381
- Keyboard Process Block Diagram
  382
  - MPUIO General-Purpose I/O Interface
    382
- GPIO Process
  383
  - GPIO Interrupt Reset
    383
- GPIO_INT Register Read Timing
  384
  - GPIO Interrupt Masking
    384
- MPU I/O Input Masking Timing
  385
  - Event Capture Module
    386
- Event Capture Process
  387
- MPU Input/Output Registers
  387
- General-Purpose Input Register (INPUT_LATCH)
  388
- Keyboard Row Inputs Register (KBR_LATCH)
  389
- Keyboard Interrupt Register (KBD _INT)
  390
- GPIO Debouncing Register (GPIO_DEBOUNCING_REG)
  391
- Block Diagram
  392
- Microwire Registers
  392
  - Microwire Interface
    392
- Transmit Data Register (TDR)
  393
- Receive Data Register (RDR)
  393
- Control and Status Register (CSR)
  394
- Setup Register 1 (SR1)
  395
- Setup Register 2 (SR2)
  397
- Setup Register 3 (SR3)
  398
- Setup Register 4 (SR4) (Read/Write)
  398
- Setup Register 5 (SR5) (Read/Write)
  399
  - Protocol Description
    400
- Behavior of a X25C02 EEPROM Read Cycle
  401
- Behavior of a XL93LC66 EEPROM Read Cycle
  401
- Read Cycle in Autotransmit Mode
  406
  - Example of Autotransmit Mode with DMA Support
    407
  - Khz Timer
    408
- Timer Interrupt Period
  409
- 32-Khz Timer Registers
  410
- Read/Write Synchronization
  410
- Timer Control Register (CR)
  411
- Tick Value Register (TVR)
  411
- Tick Counter Register (TCR)
  411
- PWL Block Diagram
  412
  - Pseudonoise Pulse-Width Light Modulator
    412
- PWL Registers
  413
  - Pulse-Width Tone
    414
- PWT Block Diagram
  415
- PWT Registers
  415
- PWT Frequency Control Register (FRC)
  416
- PWT Volume Control Register (VRC)
  416
- PWT General Control Register (GCR)
  416
  - PWT Programming
    416
- Buzzer Frequencies
  417
- Buzzer Volume
  418
- I2C System Overview
  419
  - Inter-Integrated Circuit Controller
    419
- Signal Pads
  420
- Start and Stop Conditions
  421
- I2C Data Transfer Formats
  423
- Arbitration Procedure between Two Master Transmitters
  424
- Prescale Sampling Clock Divider Value
  427
- I2C Registers
  429
- Register Access Ready (ARDY) Set Conditions
  435
- Interrupt Code (INTCODE) Conditions
  437
- Operating Modes
  442
- Repeat Mode Conditions
  442
- STT Settings
  443
- TMODE Settings
  447
  - Programming
    449
- Setup Procedure
  450
  - Flowcharts
    450
  - Master Transmitter Mode, RM = 1
    451
- Master Receiver Mode, RM = 1, Polling
  452
  - Receive Data Fixed)
    452
- Master Receiver Mode, RM =1 , Polling
  453
  - Variable, Data Contents Dependent)
    453
- Master Transmitter Mode, RM
  454
- Master Receiver Mode, RM = 0, Polling
  455
- Master Transmitter Mode, RM = 0, Interrupt
  456
- Master Receiver Mode, RM = 0, Interrupt
  457
- Master Transmitter Mode, RM = 0, DMA
  458
- Master Receiver Mode, RM = 0, DMA
  459
- Slave Transmitter/Receiver Mode, Polling
  460
- Slave Transmitter/Receiver Mode, Interrupt
  461
- LED Pulse Generator Block Diagram
  462
- LED Pulse Generator Receive and Transmit Registers
  463
  - LPG Design
    463
- LPG Control Register (LCR)
  464
- LED Blinking Period
  464
- LED on Time
  465
- Power Management Register (PMR)
  465
- Mcbsp2
  466
- Mcbsp2 Pin Descriptions
  467
- Mcbsp2 Registers
  467
- Mcbsp2 Interface Diagram
  469
- Communication Processor Data Interface
  470
  - Mcbsp2 Application Example: Communication Interface
    470
- Pin Control Register Configuration
  471
- Receive Control Register 1 Configuration
  472
- Receive Control Register 2 Configuration
  472
- Transmit Control Register 1 Configuration
  472
- Transmit Control Register 2 Configuration
  473
- Waveform Example
  474
- Pin Control Register Configuration
  475
- Receive Control Register 1 Configuration
  476
- Receive Control Register 2 Configuration
  476
- Transmit Control Register 1 Configuration
  476
- Transmit Control Register 2 Configuration
  477
- Waveform Example
  478
- USB Function Registers
  479
  - USB Function Overview
    479
- MMC/SD Host Controller Environment
  482
  - MMC/SD Host Controller Features
    484
- MMC/SD Signal Pads
  485
  - MMC/SD Host Controller Clocks and Reset
    486
- MMC_DAT Pullups
  487
  - MMC/SD Internal Pullups
    487
- MMC/SD Registers
  488
- MMC Command Register (MMC_CMD)
  489
- MMC Argument Low Register (MMC_ARGL)
  492
- MMC System Configuration Register (MMC_CON)
  493
- Clock Control
  495
- MMC_CLK/SPI_CLK High-/Low-Time Computation
  496
- MMC System Status Register (MMC_STAT)
  497
- Response Types
  498
- MMC System Interrupt Register (MMC_IE)
  504
- MMC Command Time-Out Register (MMC_CTO)
  505
- Data Time-Out Conditions
  506
- MMC Data Time-Out Register (MMC_DTO)
  506
- MMC Data Access Register (MMC_DATA)
  507
- MMC Block Length Register (MMC_BLEN)
  508
- MMC Number of Blocks Register (MMC_NBLK)
  509
- MMC Buffer Configuration Register (MMC_BUF)
  510
- MMC SPI Configuration Register (MMC_SPI)
  512
- SPI Mode C/S Timings Controls (POL = 0)
  514
- SPI Mode C/S Timings Controls (POL = 1)
  514
- Chip-Select Control (SPI Mode)
  515
- SPI Master Configuration Bits
  517
- MMC System Test Register (MMC_SYST)
  518
- MMC Module Version Register (MMC_REV)
  520
- MMC/SD Command Response Register 0 (MMC_RSP0)
  521
- MMC/SD Command Response Register 6 (MMC_RSP6)
  522
- Command Flow
  523
- Initialization Phase
  524
- Detail of Basic Operation
  524
- Command Transfer
  525
- Data Transfer
  526
- Data Transfer in MMC/SD Mode Example
  527
  - DMA Operation
    528
  - Local Host (Irq/Polling) Mode
    530
- RTC Clock Diagram
  531
  - Real-Time Clock
    531
- Time and Calendar Register Values
  532
  - Register Descriptions
    532
- Time and Calendar Registers and Alarm Register Access
  533
- Compensation Scheduling
  535
- IRQ Generation Waveform
  536
- Timer Interrupts
  536
- IRQ Alarm Interrupt Waveform
  537
- Positive and Negative Compensation Effect
  538
- RTC Registers
  539
  - Register Descriptions and Mapping
    539
- Seconds Register (SECONDS_REG)
  540
- Days Register (DAYS_REG)
  541
- Alarm Seconds Register (ALARM_SECONDS_REG)
  542
- Alarm Days Register (ALARM_DAYS_REG)
  543
- RTC Control Register (RTC_CTRL_REG)
  544
- RTC Status Register (RTC_STATUS_REG)
  545
- RTC Compensation LSB Register (RTC_COMP_LSB_REG)
  546
- USB Host Controller Overview
  547
- Read Timing Diagram
  553
- Reset Timing Diagram
  553
- Write Timing Diagram
  553
- Write State Machine #1
  554
- Read State Machine #1
  554
- HDQ and 1-Wire Overview
  556
  - Power-Down Mode
    556
- Memory Map Summary
  557
  - Software Interface
    557
- Registers Accessible from TIPB
  558
  - Frame Adjustment Counter
    560
- FAC Top-Level Diagram
  561
  - Synchronization and Counter Control
    561
- FAC Module Counters and Clock Synchronization
  562
- Synchronization Circuit for Frame Synchronization and Frame Start Signals
  563
- Synchronization Circuit Waveforms
  563
- FAC Registers
  564
  - FAC Interrupt
    564
- Frame Adjustment Reference Count Register (FARC)
  565
- Frame Start Count Register (FSC)
  565
- FAC Control and Configuration Register (CTRL)
  566
- FAC Status Register (STATUS)
  566
8 DSP Private Peripherals

567
- Highlight of DSP Peripherals
  568
- DSP Timers
  569
- Timer Interrupts Levels
  570
- PTV Divisors: 32-Bit Timers
  570
  - Timer Interrupt Levels
    570
- Timer Characteristics
  571
- Timer Registers
  572
- Control Timer Register (CNTL_TIMER)
  573
- Read Timer Register (READ_TIM)
  573
- Load Timer High Register (LOAD_TIM_HI)
  573
- Read Timer High Register (VALUE_TIM_HI)
  574
- DSP Timer 1 Registers
  575
- DSP Timer 2 Registers
  575
- DSP Timer 3 Registers
  575
- Watchdog Timer Interrupt
  576
- PTV Divisors: Watchdog Timer
  577
- Watchdog Timer Characteristics
  577
  - Programming the Watchdog Timer in Watchdog Mode
    578
  - Watchdog Timer Registers
    579
- Load Timer Register (LOAD_TIM)
  580
- DSP Interrupt Handler Cascade
  581
  - Interrupt Handlers
    581
- Level 1 Interrupt Mapping
  582
  - Level 1 Interrupts
    582
  - Level 2 Interrupts
    583
- Level 2 Interrupt Control Flow
  584
- Interrupt Handler Level 2 Registers
  586
- Mask Interrupt Register (MIR)
  587
- Interrupt Input Register (ITR)
  587
- IRQ Binary-Coded Source Register (SIR_IRQ)
  588
- Interrupt Level Registers (ILR0
  589
- Interrupt Control Register (CONTROL_REG)
  589
- Interrupt Level Registers (ILR0
  590
- DSP Level 2 Interrupt Mapping
  591
  - DSP Interrupt Interface
    592
- Interrupt Channel Implementation
  593
  - Level-Sensitive Interrupts
    594
- Edge-Triggered/Level-Sensitive Control Register Low
  595
- Edge-Triggered/Level-Sensitive Control Register High
  595
- Level-Sensitive Clear Low Register (RST_LVL_LO)
  596
- Level-Sensitive Interrupt Clear Commands
  597
- Level-Sensitive Clear High Register (RST_LVL_HI)
  597
9 DSP Public Peripherals

598

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