Instruction Cache; Introduction; Features; Functional Block Diagram - Texas Instruments OMAP5910 Reference Manual

Instruction Cache

4 Instruction Cache
4.1

Introduction

4.1.1

Features

4.1.2

Functional Block Diagram

30 DSP Subsystem
On the OMAP5912/10 applications processors, instructions for the C55x DSP
core can reside in internal memory or in DSP external memory. When
instructions reside in DSP external memory, the instruction cache (I-Cache)
can improve the overall system performance by buffering the most recent
instructions accessed by the DSP core.
Note:
The term DSP external memory refers to memory outside of the DSP
subsystem internal memory space. This includes program addresses in the
range of 0x02 8000 to 0xFF 8000 if the internal PDROM is enabled, or to
0xFF FFFF if the PDROM is not enabled.
For storing instructions, the I-Cache contains:
One 2-way cache. The 2-way cache uses 2-way set associative mapping
-
and holds up to 16K bytes: 512 sets, two lines per set, four 32-bit words
per line. In the 2-way cache, each line is identified by a unique tag.
Two RAM sets (1 and 2). These two banks of RAM are available to hold
-
blocks of code. Each RAM set holds up to 4K bytes: 256 lines, four 32-bit
words per line. Each RAM set uses a single tag to identify a continuous
range of memory addresses that is represented in the RAM set. Before
enabling the I-Cache, configure the I-Cache to use zero, one, or both RAM
sets.
The DSP core status register, ST3_55, contains three cache control bits for
enabling, freezing, and flushing the I-Cache (see section 4.2.4). To configure
the I-Cache and check its status, the DSP core accesses a set of registers in
the I-Cache (see section 4.6).
Figure 5 shows how the I-Cache fits into the DSP subsystem.
SPRU890A