Asynchronous 16-Bit Read Operation On A 16-Bit Width Device - Texas Instruments OMAP5910 Technical Reference Manual

Memory Interfaces
4.3.2.5 Asynchronous Read Operation
Figure 4–3. Asynchronous 16-Bit Read Operation on a 16-Bit Width Device
TC Clock
(internal)
EMIFS Ref
(internal)
FLASH.CLK
FLASH.CS_[X]
FLASH.ADV
FLASH.A(24:1)
FLASH.D(15:0)
FLASH.OE
FLASH.BE(1:0)
FLASH.RDY
4-18
Asynchronous read mode is selected by programming the RDMODE bit field
to 000 in the corresponding EMIF slow chip-select configuration register. This
is the default mode at reset.
The following characteristics describe asynchronous read mode operation.
-
The chip-select pulse width depends on the RDWST bit field of the EMIFS
chip-select configuration register. Pulse width equals:
(RDWST + 2) x EMIFS_Ref (shown as N cycles in Figure 4–3)
Chip-select minimum pulse width is (2 x EMIFS_Ref).
-
Address drive time follows FLASH.CS_[X] activation (no setup time guar-
anty). The FLASH.ADV output is asserted with the address for use with
Intel and AMD burst flash protocols.
-
Read data is latched on the same TC clock rising edge that deactivates
the FLASH.OE signal.
-
In asynchronous mode, the internal EMIFS reference clock is not provided
outside the EMIFS. The FLASH.CLK signal remains low.
-
Figure 4–3 shows typical timing for an asynchronous 16-bit read operation
on a 16-bit width device with RDWST = 4, FCLKDIV = 01.
Low
N cycles
Address valid
High
Valid data D0