Software Configuration - Texas Instruments OMAP5910 Reference Manual

4.5.2

Software Configuration

4.5.3 System Traffic Considerations
SPRU890A
Follow this procedure to configure with 2-way cache and two RAM sets:
1) Write to the appropriate control registers:
Write CE2Fh to GCR to indicate two RAM sets.
Write 000Fh to NWCR to initialize the logic for the 2-way cache.
Write 000Fh to RCR1 to initialize the logic for RAM set 1.
Write 000Fh to RCR2 to initialize the logic for RAM set 2.
2) Set the cache enable bit (CAEN) bit of DSP core status register ST3_55
to send an enable request to the I-Cache.
3) Poll the I-Cache-enabled (ENABLE) bit of ISR until ENABLE = 1,
indicating that the I-Cache is enabled. (The I-Cache is not instantaneously
enabled.)
4) Write to the RAM set tag registers:
a) Write the desired tag to RTR1. When you write to the tag register, the
tag is used to immediately fill RAM set 1 from DSP external memory.
b) Write the desired tag to RTR2. When you write to the tag register, the
tag is used to immediately fill RAM set 2 from DSP external memory.
While the I-Cache is enabled, you can write to a tag register at any time to
change the address range as necessary. Each time you load a tag register,
the corresponding RAM set is immediately filled from the selected address
range.
5) To monitor the RAM-set filling, poll the tag-valid bits:
a) When TAG_VALID = 1 in RCR1, the I-Cache is done filling RAM set 1.
b) When TAG_VALID = 1 in RCR2, the I-Cache is done filling RAM set 2.
Notes:
1) Do not write the same value to both RAM set tag registers.
2) The code that loads the RAM sets cannot be read from DSP external
memory at the same time that the RAM sets are being loaded from
memory. Therefore, place the RAM-set load code in memory that is
internal to the DSP subsystem.
All DSP subsystem accesses to DSP external memory eventually go through
the traffic controller. The access time for a DSP external memory request will
depend on the amount of competing accesses in the traffic controller, as well
as the configurations of the OMAP external memory interfaces (EMIFF and
EMIFS).
Instruction Cache
DSP Subsystem 47